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7273 Commits (6686e71bd6bc061feed07e20054b01e7eb4b7d4a)

Author SHA1 Message Date
Megan Wachs 6686e71bd6 riscv: In FESPI driver, rename 'wip' to 'tx_wait', a more descriptive name. 2016-11-14 16:14:39 -08:00
Megan Wachs 8de4ab011d riscv: Correct reading SPI Flash ID 2016-11-07 20:42:43 -08:00
Megan Wachs 05b12c5c20 riscv: Add first cut of Flash driver for Freedom E platforms. Completely untested. 2016-11-04 19:43:53 -07:00
Tim Newsome e51b0360f5 Make fpu regs work even if mstatus.fs is 0. 
Change-Id: I2c283f2de226518ab9a4e0476edada51825b2993
 2016-11-01 12:58:37 -07:00
Tim Newsome e7a745ed3b Fix bug with slow targets. 
Halting didn't work right in slow targets, because some code assumed the
register cache is valid before it was guaranteed to be.

Also made dbus_busy_delay and interrupt_high_delay grow faster, so that
on slow targets it takes less time to learn the correct values.

Change-Id: I948a49d4e3cd0638f5449ab94994406319fd5f42
 2016-10-27 13:00:26 -07:00
Tim Newsome e6e2070692 Add some comments. 
Change-Id: Icd7d5eb370c6c893ec4717c92249f35fb100370a
 2016-10-24 14:21:34 -07:00
Tim Newsome 3eb6cf0fc0 Make CLI step and resume work. 
Change-Id: I027d7032800f909e8d149ed84c11b6e75b75491f
 2016-10-20 14:49:23 -07:00
Tim Newsome 9b0be80d1e Use reg_cache structure, to make reg command work. 
Change-Id: I9f1d1f2eab66822c3c47284aa91b52cc34998381
 2016-10-20 10:42:28 -07:00
Tim Newsome 4eba841bfe Print when we're ready for gdb to connect. 
This should help gdbserver.py to connect reliably to really slow targets
(ie. simulators).

Change-Id: I8e9adbaf2ebde11b44e15582f036622a2d00c1f9
 2016-10-14 12:40:52 -07:00
Tim Newsome 3f6c2a9f78 Be quiet when the target is just running normally. 
Change-Id: I7861f16ba6b1b5c1851787ce5d78c02aff0568f6
 2016-10-13 10:51:53 -07:00
Tim Newsome cb93bb9035 Use an easily changed constant for timeout. 
Change-Id: I7aace463b0bd9916580e950d60b2940879b27b2a
 2016-10-11 16:26:19 -07:00
Tim Newsome 4882de94cc Display pc to the user in 'monitor reset init'. 
Change-Id: Ifb8df31954dfc5a3badef4f0a29eb510a97310a2
 2016-10-10 08:22:51 -07:00
Tim Newsome a08cef7633 Change invalid access from error to user message. 
It's not a failure in the debugger or even a real problem if a user asks
to access memory that's not accessible.

Change-Id: I30b8424d5265d1996fe4826012ed160a83f0bc6c
 2016-10-03 08:15:04 -07:00
Tim Newsome e273e23f41 Fix off-by-one error in assert. 
Also only do work for debug RAM that actually exists on the target
(exposing the off-by-one error on 32-bit targets).

Change-Id: I37e0005b6a70e949286f1d6494716f3abea03c12
 2016-09-29 10:40:50 -07:00
Tim Newsome 4dbc9962d3 Clear dmode triggers when we first halt the target 
This helps repeated runs of the testsuite pass, and is probably a good
idea in general.

Change-Id: I89ed167968f8b8817c66f1718f374d0c502780c7
 2016-09-29 10:23:46 -07:00
Tim Newsome 78fe0b56db Deal with dbus being busy in all cases. 
Change-Id: Ifede6e05c3c4538f22a52cd0e9833cf3a9983d04
 2016-09-29 08:28:31 -07:00
Tim Newsome b04d5e8821 Read idle, and test all debug RAM. 
Read dtmcontrol's idle field to decide how many run-test/idle cycles are
required to communicate with the target.

In riscv_examine(), write and read all of Debug RAM to check the target
is at least somewhat sane.

Change-Id: Ieedb7a50418fa1f5e0d456cde53c52f7fc51662b
 2016-09-27 13:06:32 -07:00
Tim Newsome c67850b63d Only write to existing dram. Clear dbus error. 
Old code would write 64 bytes of DRAM if the dbus was busy in
cache_write().

New code clears the dbus error condition when the bus is busy. (This
part is untested.)

Change-Id: Ia396fe819fa1828bb75726d85513b113cc9e13f0
 2016-09-27 08:45:51 -07:00
Tim Newsome 54c65a9a4b Improve low-level logging. 
Now logging is consistent and more readable.
I did remove most logging during riscv_poll() since it clutters up the
log/screen and is not generally helpful.
 2016-09-23 14:16:24 -07:00
Tim Newsome 08228e6f53 Make more code use the scans "class". 
Helps with consistency, and this is a rare commit that net deletes
lines.
 2016-09-23 14:16:24 -07:00
Tim Newsome cf1dc0b6cb Implement hardware triggers that match spec. 
It's basically working, but the following corner cases are failing:
    TriggerDmode
    TriggerLoadAddressInstant
    TriggerStoreAddressInstant
 2016-09-23 14:16:24 -07:00
Tim Newsome 526bbc5284 Optimize read a bit. 
Remove some unnecessary scans.
 2016-09-23 14:16:24 -07:00
Tim Newsome c68b13ed67 Properly mark the cache as clean after its written 
This reduces the number of scans, but I doubt it noticeably improves
performance.
 2016-09-23 14:16:24 -07:00
Tim Newsome 243233c8b8 Convert some more code for 64-bit. 2016-09-23 14:16:24 -07:00
Tim Newsome b04f89076a Properly write 64-bit PCs. 2016-09-23 14:16:24 -07:00
Tim Newsome e3e745abb9 WIP for 64-bit support. 
GPR register writes/reads seem to work.
 2016-09-23 14:16:24 -07:00
Megan Wachs 7927e90a42 Prevent the State Machine from moving during runtest 2016-09-23 14:16:24 -07:00
Tim Newsome 2f1b6b5803 Stop using conditional writes. 
It doesn't help, and makes the spec more complex. Now that I've proven
OpenOCD doesn't need it, I'll remove it from the spec.
 2016-09-23 14:16:24 -07:00
Tim Newsome 5dbad6b0c9 Check for business in block reads. 2016-09-23 14:16:24 -07:00
Tim Newsome f8b0f4bf29 Check for exceptions in reads and writes. 2016-09-23 14:16:23 -07:00
Tim Newsome f5ae4d864c Add support for virtual priv register. 
Users can use this register to inspect and change the privilege level of
the core. It doesn't make any assumptions about the actual underlying
debug mechanism (as opposed to having the user change DCSR directly,
which may not exist in all debug implementations).
 2016-09-23 14:16:23 -07:00
Tim Newsome 5de81da8f4 Remove commented out code. 
Also added back the initial check that confirms debug RAM is written
correctly.
 2016-09-23 14:16:23 -07:00
Tim Newsome a916d204b9 Optimize memory read. 
Saves 8s on the full test suite.
 2016-09-23 14:16:23 -07:00
Tim Newsome 32e7a962c3 Write fence.i before dret. 
Makes things work if the ROM doesn't contain fence.i (which is slow, so
Andrew took it out).
 2016-09-23 14:16:23 -07:00
Tim Newsome 4ced71b1f1 Log more. 2016-09-23 14:16:23 -07:00
Tim Newsome 20e2bfe3db Quickly read all GPRs on halt. 
gdb will ask for them anyway, and one by one is slow.
StepTest went from 9.7s to 5.3s.
 2016-09-23 14:16:23 -07:00
Tim Newsome 6fac5a41f8 Remove some hwbp debug code. 2016-09-23 14:16:23 -07:00
Tim Newsome 7dcc0681d4 Speed up some other operations. 2016-09-23 14:16:23 -07:00
Tim Newsome 1fdcfa7082 Speed up register read. 
Don't scan an extra sequence just to read the return value.
 2016-09-23 14:16:23 -07:00
Tim Newsome 27b94d36d0 Fix 32-bit build. 2016-09-23 14:16:23 -07:00
Tim Newsome 668070cc45 Faster download. 
16K testcase:
Transfer rate: 53 KB/sec, 2222 bytes/write.
 2016-09-23 14:16:23 -07:00
Tim Newsome 9aab0aa068 Minor cleanup. 2016-09-23 14:16:23 -07:00
Tim Newsome 06f6b5020c Use optimized cache/program write scheme for most 
operations.
 2016-09-23 14:16:23 -07:00
Tim Newsome a1875fbecf Working on optimized program running. 
Makes a big difference on the XLEN code (29ms to 8ms). Now to use it in
more places.
 2016-09-23 14:16:23 -07:00
Tim Newsome 9b9653ab7d Use hardware single step. 2016-09-23 14:16:23 -07:00
Tim Newsome eac8933b89 WIP on performance improvement. 
Also implement empty arch_state to prevent occasional startup crash.
 2016-09-23 14:16:23 -07:00
Tim Newsome 2d02e77bed Make this compile for 32-bit targets. 2016-09-23 14:16:23 -07:00
Tim Newsome aaa8ce10b8 Correctly figure out the number of extant hwbps. 2016-09-23 14:16:23 -07:00
Tim Newsome c471cfb63b Simple execute hardware breakpoint works. 2016-09-23 14:16:23 -07:00
Tim Newsome cb57aa55fa Deal with exceptions on register read. 
Cache dpc, so we can restore it when it's clobbered by an exception.
 2016-09-23 14:16:23 -07:00