Commit Graph

9136 Commits (5b2426a4b2c3d0eb244bb8ec276ef24228e9e31d)

Author SHA1 Message Date
Tim Newsome 5b2426a4b2
Deal with vlenb being unreadable. (#458)
Instead of exiting during examine(), spit out a warning, and don't
expose the vector data registers. We do provide access to the vector
CSRs, because maybe they do work? It's just that we have no idea what
the size of the data registers is.

Change-Id: I6e9ffeb242e2e22fc62cb1b50782c2efb4ace0bd
2020-03-26 09:08:56 -07:00
Jonathan Tinkham 548790fefc
Add support for HiFive1 RevB board (#456)
Adds new PID (0x1051) used on board to libjaylink, and add config
and flash entry for RevB board and FE310-G002 respectively.
2020-03-19 09:31:05 -07:00
Tim Newsome f6f30fb148
Update to 1.11 privileged spec. (#455)
Change-Id: I25029f7e83819464e71528fb4225b4761787793f
2020-03-18 12:24:22 -07:00
Tim Newsome 54e5d2533c
helper: skip including sys/sysctl.h on Linux (#450)
Starting from glibc 2.30, the header file sys/sysctl.h gets
deprecated on Linux, after the commit 744e82963716 ("Linux:
Deprecate <sys/sysctl.h> and sysctl")
	https://sourceware.org/git/?p=glibc.git;a=commitdiff;h=744e82963716

The associated NEWS reports
	The Linux-specific <sys/sysctl.h> header and the sysctl
	function have been deprecated and will be removed from a
	future version of glibc.

Latest automake 1.16.1 still does not handle this case.
Current OpenOCD build fails with warning and requires configure
with "--disable-werror" to build.

Prevent including sys/sysctl.h on Linux build.

Change-Id: I5310976573352a96e5aef123352f73475f0c35fe
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5317
Tested-by: jenkins
Reviewed-by: Moritz Fischer <moritz.fischer.private@gmail.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>

Co-authored-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-03-05 12:13:33 -08:00
Tim Newsome 1ae21b3874
Fix address translation when high bits are set. (#453)
Fixes #452.
Also check that the high bits match the MSB of the virtual address.

Change-Id: Ib1d3d04db9ad9327ef71ea3736d5cf5d3b65b9c4
2020-03-05 11:33:51 -08:00
Tim Newsome 1449af5bdb
Give control over dcsr.ebreak[msu] bits. (#451)
This allows a user to debug code that uses software breakpoints itself.

Change-Id: If40cb626354e11703017cdf8c5919a31e83ebc3f
2020-02-20 13:58:15 -08:00
Tim Newsome 95462a8a35
Add support for vector register access (#448)
* WIP

Change-Id: I0264a73b7f7d2ce89cc0b80692dbf81d9cdcc2fd

* Reading v* registers appears to work.

Can't really test it though, because gdb doesn't print them right.

Change-Id: I8d66339371c564a493d32f15c3d114b738a455c5

* Total hack to communicate registers to gdb.

Change-Id: Id06c819675f2a5bcaf751e322d95a7d71c633765

* Implement writing vector registers.

Fixed reading vector registers.

Change-Id: I8f06aa5ee5020b3213a4f68644c205c9d6b9d214

* Show gdb the actual size of the vector registers.

This length may be different per hart.

Change-Id: I92e95383da82ee7a5c995822a53d51b1ea933493

* Remove outdated todo comment.

Change-Id: Ic9158b002858f0d15a6452773b095aa5f4501128

* Removed TODO comment.

Filed #449 to track this.

Change-Id: I5277b19e545df2024f34cda39158ddf7d0d89d47

* Nicely handle some errors reading/writing V regs.

Change-Id: Ia7bb63a5f9433d9f7b46496b2c0994864cfc4a09
2020-02-14 14:54:05 -08:00
Tim Newsome 7cb8843794
Update the current thread when gdb requests a step. (#444)
Evidently this is what gdb expects.

Change-Id: I634cdbcbcfab149c1b916e3744ff4915a8f8669b
2020-01-31 12:56:46 -08:00
Tim Newsome 2f456abd55
Complain about debug version before authentication. (#441)
Change-Id: I769af8323545c2c18e4253a1543e9202f0bdfabc
2020-01-27 16:07:08 -08:00
Tim Newsome 69e6891434
Handle DMI busy in sba write. (#437)
* Handle DMI busy in sba write.

If we encounter DMI busy on the NOP after a read, we'll never get the
value out because DMI busy is sticky. The read must be retried, but we
don't know whether it was ever issued. Since the read has side effects
(incrementing of the address) this retry must be handled at a higher
layer. So now dmi_op_timeout can be told to retry or not, and if retry
is disabled it'll return an error when busy.

Also actually properly do the retry in dmi_op_timeout(). Previously the
code would not reissue the command and end up returning a garbage value.

Change-Id: I3b52ebd51ebbbedd6e425676ac861b57fbe711b1

* Fix whitespace.

Change-Id: Icb76d964e681b22346368d224d1930c9342343f3

* Handle a few more DMI busy cases.

Change-Id: I8503a44e4bf935c0ebfff0d598fe4c322fda702a

* Explain when to use dmi_op_timeout(retry).

Change-Id: I1a5c6d76ac41a84472a8f79faecb2f48105191ff

* dmi_reset does not affect the current transaction.

That means the retry scheme we had been using works fine. This does
contain some minor tweaks, and now we pass my tests which hammer the DMI
busy case harder.

Change-Id: I13eee384dbba82bc5a5b1d387c75c547afe557b5

* Remove unnecessary changes to make the PR readable

Change-Id: I87079876e6965563cf590e3936b3595aeab8715d

* Move idle to end of line...

... because we go through run-test/idle after the scan.

Change-Id: I21a8cff22471f0b895d8cd8d25373dced9bf1ca9

* Remove unused code.

Change-Id: I07a7cdd2d64ca40a4fe181111a34cf55ff1928d1
2020-01-13 15:10:43 -08:00
Jan Matyas fcea4f79ba Don't issue extra FENCE+FENCE.i for the current hart. (#439)
The original OpenOCD code issued FENCE & FENCE.i twice for the current
hart (which is harmless, but takes time).

Avoiding this extra FENCE is a slight performance improvement. Per my rough
measurements, this improves performance of certain debugger actions
(single-stepping) by approx. 20% in single-hart systems.
2020-01-10 12:29:10 -08:00
Tim Newsome 8b8db033ee
Upcast mask value to work with 64-bit physical (#436)
Change-Id: I00f0d2a3c79a431e1aa49c7478fa6c17e2fa5256
2020-01-06 16:57:15 -08:00
Hsiangkai 2c3f099b73 Fix bugs. Do not touch SATP if there is no MMU. (#435)
* riscv: Fix bugs. Do not touch SATP if there is no MMU.

In some platform, there is no SATP register at all.
OpenOCD will report unexpected errors if SATP is unreadable.
So, use 'riscv_enable_virtual' to guard SATP access.

* riscv: fix format typo.
2019-12-31 11:27:22 -08:00
Hsiangkai 9886f77374 riscv: translate virtual address to physical address. (#425)
* riscv: translate virtual address to physical address.

* riscv: fix formatting errors.

* riscv: fix build errors.

* riscv: Remove redundant command for virtual address access.

* Revert "riscv: Remove redundant command for virtual address access."

This reverts commit 990d09eac37d2effcfc5c0d0b5c99678f45e7d7f.

* riscv: Change command disable_virt2phys  to set_enable_virt2phys

1. Avoid double negative logic to make users easy to use.
2. Add document about new comomand 'riscv set_enable_virt2phys on|off'
2019-12-10 12:18:03 -08:00
bluew aec5cca15b Increase maximum number of harts (#429)
OpenOCD can't deal with systems that have more than 32 harts.
2019-12-05 17:22:12 -08:00
Tim Newsome 780d8e4d3e
Remove unused data structure. (#431)
Saves 1.4MiB of RAM too, with just 1 hart configured.

Change-Id: I68d8c003a67c280b62ff6c9285ac6f54865f99f2
2019-12-04 16:23:22 -08:00
Tim Newsome 50d0c2f67c
Warn about using `-rtos riscv`. (#430)
Change-Id: I7fc5dc0ebe91497ffdefe480a409dc0feacfb49f
2019-12-04 12:22:49 -08:00
Jan Matyas e03dd199e0 Fixed write_memory_progbuf() on RV64. (#426)
Abstract write size (aarsize) to shall always match the real
size of the register. This is because abstract write of smaller size
than the register need not be supported per spec (pg. 13 of RISC-V
External Debug Support ver. 0.13.2).
2019-11-27 15:24:25 -08:00
Tim Newsome de00906ebd
Fix memory access on some targets. (#428)
Fix memory access on 64-bit targets with no progbuf and sba that
supports 32-bit accesses but not 64-bit accesses. Bug was introduced in #419.

This fixes https://github.com/riscv/riscv-tests/issues/217.

Change-Id: Ib5ddf9886b77e3d58fe1d891b560ad03d5a46da1
2019-11-22 11:37:46 -08:00
Jan Matyas 739d16d503 Fix: Take into account progbuf writability. (#424)
When allocating scratch memory within RISC-V target
(scratch_reserve()), take into account whether progbuf
is writable or not, as determined by examine_progbuf().
2019-11-20 12:00:00 -08:00
Tim Newsome e944de422e
fespi: Properly support large flash devices (#421)
* 64-bit progbuf memory reads work.

Change-Id: Ia3dbc0ee39a31ed0e5c38bbb3d9e089b2533f399

* 64-bit writes work.

Change-Id: Iae78711d715b6682817bb7cce366b0094bda8b23

* Let targets indicate number of supported data bits.

This is used by the default memory read/write functions when creating an
aligned block.

I'm adding this mainly to ensure I get coverage of the 64-bit progbuf
memory read/write code.

Change-Id: Ie5909fe537c9ec3360a8d2837f84be00a63de77b

* Make mingw32 happy.

Change-Id: Iade8c1fdfc72ccafc82f2f34923577032b668916

* WIP >16MB flashing.

Change-Id: Ibef9244f8573d2fbf19b80e5db7c2d3a10da59b5

* >16MB flashing works on Hi5 Unleashed

But now flashing HiFive1 is broken.

Change-Id: If939c9e21cf793ae727f3335205abd261a998c0c

* Fix off-by-one error on bank size.

Change-Id: I0e6e49db8c1bfddb2c5f67d40f62111246db8dcb

* Fix formatting.

Change-Id: I4211f9328c7d11ea659be9588a81aa2cd59017f9
2019-11-15 12:50:08 -08:00
Greg Savin b7bd3f8d47 BSCAN batch fix (#422)
* fix for batch scans not honoring presence of BSCAN tunnel

* fix formatting to placate checkpatch

* replace DIM with ARRAY_SIZE

* Refactor code that adds a bscan tunneled scan.

* Move bscan tunnel context to the batch structure, and in array
form, one per scan

* adjust code that was inconsistent with project code formatting standards
2019-11-12 09:00:35 -08:00
Tim Newsome f93ede5401
Add support for 64-bit memory reads/writes (#419)
* 64-bit progbuf memory reads work.

Change-Id: Ia3dbc0ee39a31ed0e5c38bbb3d9e089b2533f399

* 64-bit writes work.

Change-Id: Iae78711d715b6682817bb7cce366b0094bda8b23

* Let targets indicate number of supported data bits.

This is used by the default memory read/write functions when creating an
aligned block.

I'm adding this mainly to ensure I get coverage of the 64-bit progbuf
memory read/write code.

Change-Id: Ie5909fe537c9ec3360a8d2837f84be00a63de77b

* Make mingw32 happy.

Change-Id: Iade8c1fdfc72ccafc82f2f34923577032b668916
2019-11-04 11:04:30 -08:00
Tim Newsome 20804cb4d2
pmpcfg[13] only exist on RV32. (#416)
Change-Id: I38f10d34b163eb7d0bf44b5717bbb027b0e43e76
2019-10-23 11:37:51 -07:00
Tim Newsome 0409bf9b24
Merge pull request #417 from riscv/heterogeneous
Combine SMP group registers into one list for gdb
2019-10-14 12:18:52 -07:00
Tim Newsome 885260505a Combine SMP group registers into one list for gdb
This makes behavior when you've configured an SMP group of heterogeneous
targets a bit less weird. (You still shouldn't be doing that, since gdb
and who knows what else assumes that the targets in an SMP group are
homogeneous.)

Specifically, if you have a HiFive Unleashed board (where the first core
is fairly basic and the other 4 or more full-featured) this lets you
connect to all 5, and still have access to the FPU etc. on the higher
numbered cores.

Change-Id: I2e01f63f8753f78c29d7f414ea603e02bf0390e0
2019-10-11 15:51:35 -07:00
Tim Newsome 91d00468b6
Merge pull request #413 from riscv/compliance
The compliance test is poorly supported.
2019-10-09 11:41:29 -07:00
Tim Newsome 3b4fcf471f The compliance test is poorly supported.
In reaction to #412.

Change-Id: I183bd8b4995c04e44cbc4f1c475eae391030fae6
2019-10-03 16:36:24 -07:00
Tim Newsome 7c82a7b9d5
Merge pull request #411 from riscv/from_upstream
Get latest code from upstream
2019-09-30 13:23:19 -07:00
Tim Newsome f9bc528478 Fix filterdiff line.
We don't want to enforce code style on libjaylink, which in mainline is
a subrepository.

Change-Id: Ic72dff4b56f5781dd1ba94519eb4b067903ceaae
2019-09-30 12:47:34 -07:00
Tim Newsome 1107dc7e3f Fix the build.
Change-Id: I3a314488136ec47611d660140fb5dd70c00be59c
2019-09-27 16:35:03 -07:00
Tim Newsome 53b87ddfc5 Update libjaylink.
Change-Id: I9b8d7a5b9356c962d625e541f917c5dd74f47a98
2019-09-27 12:12:32 -07:00
Tim Newsome 9aac179cf2 Merge branch 'master' into from_upstream
Change-Id: I036350ee06aa396344fb8a80c7dba148ec24c9c8
2019-09-27 12:07:00 -07:00
Tim Newsome bbdc28e0f5
Use more idiomatic assembly for flash code. (#410)
Also change the address that we use to link the PIC code, so that if
there is a PIC issue in the future it will show up on hardware I test
against.

Also remove fespi.S, which hasn't been used in a long time.

Change-Id: I667d930b48107a3522d619167c7afc335431b4b6
2019-09-25 11:51:07 -07:00
darius-bluespec 20fc862b15 Perform SBA writes with batch transactions for improved performance. (#405)
* Add riscv_batch_available_scans().

This function will query the number of available scans in a batch.

* Perform SBA writes with batch transactions for improved performance.

Using batch transactions avoids an unnecessary dmi read after every
dmi write, resulting in a significant performance improvement.
2019-09-24 17:49:25 -07:00
Seth LaForge 3110092720 src/jtag/aice: Fix obviously incorrect bit op.
Fix expression "(pin_status | 0x4)" which was always true rather than
testing a bit. Untested - was clearly not expressing the intent of the
author by inspection. Found by automated tooling and rtrieu@google.com.

Signed-off-by: Seth LaForge <sethml@google.com>
Change-Id: I4bb91e60e8ce9757bf21976cc48de6f85a39c68d
Reviewed-on: http://openocd.zylin.com/5301
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-09-24 05:47:43 +01:00
Christopher Head 31a3324b68 helper/command: clear errno before calling parser
The C standard says that errno is set to ERANGE if an out-of-range value
is returned by strtol, strtoul, et. al., but it does not say that errno
is cleared if the function is successful (and, indeed, it is not on
glibc). This means that, if errno is ERANGE before strtol is called, and
if the value to be converted is exactly the maximum (or, for a signed
conversion, the minimum) legal value, COMMAND_PARSE_NUMBER will
erroneously indicate that the value is out of range.

Change-Id: I8a8b50a815b408a38235968f1c1d70297ea1a6aa
Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/5298
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-09-24 05:47:18 +01:00
Marc Schink 181d594205 flash/nor/tcl: Fix usage of 'flash erase_sector' command
Change-Id: I2141e377a0531cab8d1140049a2ee7721d30cfdc
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/5299
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-09-24 05:46:52 +01:00
Tim Newsome bf1e201336
The stack is relative to the program. (#409)
Just like everything else. Fixes flashing on targets that don't have RAM
at 0x80000000.

Change-Id: Ibf423c95ba333660e760d5110f5ce2375c1b762c
2019-09-23 15:51:17 -07:00
Marc Schink 85a460d5a3 tcl/board: Add Rigado BMD-300 Evaluation Kit
Change-Id: Iba8e12818e2041e51214dab413eb57f0e5bf3f75
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/5218
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2019-09-20 07:27:27 +01:00
Khem Raj 101345270b esirisc_flash: Rename PAGE_SIZE to FLASH_PAGE_SIZE
PAGE_SIZE is defined in system includes on some systems, this would
avoid the unintended conflict

Fixes
| src/flash/nor/esirisc_flash.c:95:9: error: 'PAGE_SIZE' macro redefined [-Werror,-Wmacro-redefined]
| #define PAGE_SIZE                       4096
|         ^
| /mnt/a/yoe/build/tmp/work/core2-64-yoe-linux-musl/openocd/0.10+gitrAUTOINC+7ee618692f-r0/recipe-sysroot/usr/inclu
de/limits.h:89:9: note: previous definition is here
| #define PAGE_SIZE PAGESIZE

Change-Id: I195b303fc88a7c848ca4e55fd6ba893796df55cc
Signed-off-by: Khem Raj <raj.khem@gmail.com>
Reviewed-on: http://openocd.zylin.com/5180
Tested-by: jenkins
Reviewed-by: Steven Stallion <sstallion@gmail.com>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2019-09-18 07:05:08 +01:00
Greg Savin c5bb7fb230
Add TCK padding in the OSCAN1 reset/online/activate sequence. (#406) 2019-09-13 12:50:36 -07:00
Tim Newsome 11e6127401
Display IDCODE in message about it not existing. (#404)
Change-Id: I1d1ca10ec62502c4757b64122e190ff964616684
2019-09-11 10:48:18 -07:00
Tim Newsome 274be9587f
Fix flashing HiFive Unleashed (#402)
* Align algorithm stack to XLEN.

This fixes algorithm timeout on RV64 targets.
Also improve debug information in various places.

Change-Id: Id3121f9c6e753c6a7e14da511e4de0587a6f7b4d

* Compile 32-bit RISC-V algorithms for RV32E.

Change-Id: I33a698c0c6ba540de29fa0459242c72a67b0cbaa

* Remove debug code.

Change-Id: I37c966ce0f2d1fe68cd6ae0724d19ae95ebaf51b

* Dump start of gdb packets escaping non-printable.

Change-Id: Ie5f36b5c9041bfc0e5aa9543f0afe2c4810c2915

* Propagate flash programming errors.

Change-Id: I0c938ce7a1062bcc93426538cbc82424000f37b7

* Improve debug messaging.

Change-Id: I47ac3518f3b241986c677824864102936100adf6

* Add debug output to flash image.

This is helpful when you're debugging the flash algorithm itself, and a
nop when running it through OpenOCD.

Change-Id: Id44c6498c288872cc2cec79044116ac38198c572

* Make timeout depend on how much data is written.

Change-Id: I819efa04cd6f6bd6664afd5c53cc7a8a5c84f54e

* Fix issi erase commands.

This is required to flash HiFive Unleashed.

Change-Id: I33e4869d1d05ca8a1df6136bccf11afda61bfe10

* Fix running algorithm on multicore `-rtos riscv`.

The bug was that poll() might change the currently selected hart, and in
that case we'd access registers on that other hart after the algorithm
is finished.

Change-Id: I140431898285cf471b372139cef2378ab4879377

* Make fespi flash algorithm debugging optional.

Also add a scheme that allows you to see the stack trace of where a
failure occurred if debugging is enabled.

Change-Id: Ia9a3a9a941ceba0f8ff6b47da5a8643e5f84b252
2019-09-09 12:01:17 -07:00
Tarek BOCHKATI 09eb941cb8 flash/nor/stm32h7x: remove unused 'pages_per_sector' from stm32h7x_part_info
Change-Id: I1b79c25cada574e3a9849f506443c836bd707604
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5289
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Christopher Head <chead@zaber.com>
2019-09-08 11:55:19 +01:00
Tarek BOCHKATI 5b06b88af8 flash/nor/stm32h7x: remove flash size information from device name
There is no sense in displaying the max size (2M) as there is variants
of this device with reduced flash size

Change-Id: I40574064d75fdf2a038044c81038a6d7abc6c4dd
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5288
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Christopher Head <chead@zaber.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-09-08 11:54:34 +01:00
Caleb Szalacinski 5a235226f0 flash/nor: flash driver for Synwit SWM050 MCUs
SWM050 is a series of MCU product by Foshan Synwit Tech, which is
available in TSSOP-8 or SSOP-16 packages.

Adds flash driver for the internal 8KiB flash of the MCU. The registers
are based on reverse engineering the J-Flash blob provided by the
vendor.

Also adds a pre-made cfg file.

Change-Id: I0b29f0c0d062883542ee743e0750a4c6b6609ebd
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Caleb Szalacinski <contact@skiboy.net>
Reviewed-on: http://openocd.zylin.com/4927
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2019-09-08 11:53:12 +01:00
Han Hartgers 642a9310ca target/dsp563xx: dsp563xx restore reg support
Added "exist=true" field to the reg_list struct to make access to the
dsp563xx registers again possible. Without it defaults to exist=false
and all the reg related functions will return nothing.

Fixes regression from b5964191f0

Change-Id: I9c256346735b8d66919c4ba83f528a8afca46ff9
Signed-off-by: Han Hartgers <han.hartgers@gmail.com>
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5239
Tested-by: jenkins
2019-09-08 11:52:06 +01:00
Seth LaForge 844c82934e src/flash/nand: Fix some operator precedence bugs.
Fix two expressions where precedence of operator | vs ?: was clearly confused.
Untested - was clearly not expressing the intent of the author by inspection.
Found by automated tooling and rtrieu@google.com.

Change-Id: I46f190154797f8affc761caf3a15a1a9db53d702
Signed-off-by: Seth LaForge <sethml@google.com>
Reviewed-on: http://openocd.zylin.com/5281
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2019-09-08 11:51:21 +01:00
Tim Newsome 24d59cfb90
Update jep106.inc by running the script. (#400)
Script was actually run by Ken Pettit, so he can get IQ-Analog in there.

Change-Id: If0db2f624f2081a92749e39832f9000b74ef8844
2019-09-07 11:38:15 -07:00