Commit Graph

7692 Commits (41017409284f821b5a3d377b8fc7230c32ffe75d)

Author SHA1 Message Date
mwachs5 4101740928 riscv: add compliance tests for DPC and DCSR 2017-06-28 19:36:22 -07:00
mwachs5 e17ca3a31d riscv: More compliance tests for core registers. 2017-06-28 19:36:22 -07:00
mwachs5 222850df55 debug: add a 'wfi' to compliance test. 2017-06-28 19:36:22 -07:00
mwachs5 9e76ec1779 riscv: Compliance test for HALTREQ/RESUMEREQ R/W 2017-06-28 19:36:22 -07:00
mwachs5 ccc605158a riscv: Added several compliance test items 2017-06-28 19:32:38 -07:00
mwachs5 95ee7975ea riscv: Add skeleton of RISC-V v013 compliance 2017-06-28 19:32:38 -07:00
Megan Wachs 7a4948c126 riscv: initial checkin of a 'compliance test' command. 2017-06-28 19:32:38 -07:00
Palmer Dabbelt 4e2e730abe Merge pull request #68 from riscv/multicore
Testsuite now passes on multicore target
2017-06-20 14:20:00 -07:00
Tim Newsome 9cd98058a0 Set hardware triggers on all harts.
Right now we're using "threads" to represent harts. gdb/OpenOCD assume
there's only one set of hardware breakpoints among all threads. Make it
so.
2017-06-20 13:10:35 -07:00
Tim Newsome 10518351bb Don't immediately segfault with -rtos on v0.11. 2017-06-20 11:32:42 -07:00
Tim Newsome ccdd26e3ef Comment curious code. 2017-06-20 11:32:42 -07:00
Tim Newsome 927f9d8873 Update list of "threads" when harts are discovered.
This ensures that "info threads" is accurate as soon as gdb connects.
Also print out number of triggers that is discovered in examine().
2017-06-20 11:32:42 -07:00
Tim Newsome 8d79a7c18b Merge pull request #67 from riscv/cosmetics
Various cosmetic improvements
2017-06-20 11:32:17 -07:00
Tim Newsome 4d264b3579 Put early DEBUG notice of XLEN back. 2017-06-19 08:46:02 -07:00
Tim Newsome 6082f35a55 Update debug_defines. Clarify debug output.
Update debug_defines from the spec, commit 920ec9a690.
Decode dmstatus scans in the debug output.
2017-06-16 14:02:25 -07:00
Tim Newsome fd81f7fcac Fix comment. 2017-06-16 14:02:25 -07:00
Tim Newsome 851849a295 Tell the user about detected harts. 2017-06-16 14:02:25 -07:00
Tim Newsome 3abb347bd9 Tighten up debug output.
Assuming the program allocating code works, we don't need its output.
Only output parts of the debug RAM that are actually doing something.
2017-06-16 14:02:25 -07:00
Tim Newsome 91c3dcc197 Merge pull request #66 from riscv/whitespace
Fix indentation to match OpenOCD style.
2017-06-16 13:07:46 -07:00
Tim Newsome ac2da40f74 Fix indentation to match OpenOCD style.
This change is just in the whitespace. There are no code changes.

See http://openocd.org/doc-release/doxygen/stylec.html
2017-06-15 12:44:50 -07:00
Tim Newsome 363a0a2bf2 Merge pull request #64 from riscv/release-fixes
Two fixes from the release branch
2017-06-15 12:43:46 -07:00
Palmer Dabbelt e17f8f03b5 Merge pull request #65 from riscv/print64
Fix print statements to work with 64-bit addresses
2017-06-15 12:35:07 -07:00
Tim Newsome 50a223ef9a Fix print statements to work with 64-bit addresses 2017-06-15 12:24:37 -07:00
Palmer Dabbelt afc9eb6c47 Jump to the RTOS hartid after halting
When I disappeared the polls everywhere I forgot to sanitize the hartid
after halting.  This is an invariant that GDB expects: when you return
from a halt whatever thread is marked as currently selected is the
thread that the next register accesses reference.
2017-06-15 12:16:33 -07:00
Palmer Dabbelt 099a3020d2 Clear abstract errors from register_read_direct 2017-06-15 12:16:24 -07:00
Palmer Dabbelt 1a69308621 Merge pull request #63 from riscv/crc64
Accept 64-bit addresses in CRC requests.
2017-06-15 12:15:49 -07:00
Tim Newsome 503da094e8 Accept 64-bit addresses in CRC requests. 2017-06-15 10:44:37 -07:00
Palmer Dabbelt ecc181d12d Merge pull request #62 from riscv/riscv64
Merge mainline OpenOCD
2017-06-14 17:02:04 -07:00
Tim Newsome 64af052911 Fix the build.
Main change is to make riscv_addr_t be unsigned. The rest is mechanical
fixing of types, print statements, and a few signed/unsigned compares.

Smoketest indicates everything is working more or less as before.
2017-06-13 12:33:01 -07:00
Tim Newsome 845c2f6b69 Merge branch 'remotes/openocd/master' into riscv64
Merged 1025be363e

Conflicts:
	src/flash/nor/Makefile.am
	src/rtos/Makefile.am
	src/rtos/rtos.c
	src/target/Makefile.am
	src/target/target.c
	src/target/target_type.h

Doesn't build yet, but I fixed the conflicts that git pointed out.
2017-06-13 11:52:50 -07:00
Tim Newsome 7af58e6283 Merge pull request #60 from riscv/tim
Fix dmi_read() indentation; remove \n in LOG_ERROR
2017-06-08 12:39:30 -07:00
Tim Newsome 6be600318c Fix dmi_read() indentation; remove \n in LOG_ERROR 2017-06-08 12:31:08 -07:00
Megan Wachs c3b344d1c0 riscv: Move the initialization of the field inside the structure for consistency 2017-06-07 21:06:33 -07:00
Megan Wachs 459b39ec67 riscv: v13 -- dmi_write must still check for the OP result 2017-06-07 21:06:33 -07:00
Tim Newsome 11008baee3 %p already includes 0x (on gcc) 2017-06-06 11:51:15 -07:00
Tim Newsome 83afb93004 Don't leave fd undefined.
When gcc isn't optimizing well, it might not realize that it's not
possible to return fd without initializing it, and then the build fails
due to -Werror.
2017-06-06 11:51:15 -07:00
Paul Fertser 1025be363e flash: nor: ath79: fix build failure due to recent MIPS changes
Change-Id: I7139b0658f048afea2d16216c93e8946356a630d
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/4151
Tested-by: jenkins
Reviewed-by: Salvador Arroyo <sarroyofdez@yahoo.es>
2017-06-02 20:20:26 +01:00
Tobias Diedrich 6b9d19d367 flash: Add support for Atheros (ath79) SPI interface
Supported SoCs: AR71xx, AR724x, AR91xx, AR93xx, QCA9558

Extended and revised version of my original patch submitted by Dmytro
here: http://openocd.zylin.com/#/c/3390

This driver is using pure SPI mode, so the flash base address is not
used except some flash commands (e.g. "flash program") need it to
distinguish the banks.

Example config with all 3 chip selects:
flash bank flash0 ath79 0 0 0 0 $_TARGETNAME cs0
flash bank flash1 ath79 0x10000000 0 0 0 $_TARGETNAME cs1
flash bank flash2 ath79 0x20000000 0 0 0 $_TARGETNAME cs2

Example usage:
> flash probe flash0
Found flash device 'win w25q128fv' (ID 0x001840ef)
flash 'ath79' found at 0x00000000
> flash probe flash1
No SPI flash found
> flash probe flash2
No SPI flash found
> flash banks
> flash read_bank flash0 /tmp/test.bin 0x00000000 0x1000
reading 4096 bytes from flash @0x00000000
wrote 4096 bytes to file /tmp/test.bin from flash bank 0 at offset
0x00000000 in 28.688066s (0.139 KiB/s)

Change-Id: I5feb697722c07e83a9c1b361a9db7b06bc699aa8
Signed-off-by: Tobias Diedrich <ranma+openocd@tdiedrich.de>
Reviewed-on: http://openocd.zylin.com/3612
Tested-by: jenkins
Reviewed-by: Dmytro <dioptimizer@hotmail.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-05-31 08:18:29 +01:00
Grzegorz Kostka 83c67b7ac7 imx_gpio: add mmap based jtag interface for IMX processors
For some targets (like nrf51) sysfs driver is too slow. This
patch implements memory maped driver for IMX processors.
Mostly based on bcm2835gpio. Tested on imx6ul CPU. However, it should
work on any NXP IMX CPU.

Change-Id: Idace4c98181c6e9c64dd158bfa52631204b5c4a7
Signed-off-by: Grzegorz Kostka <kostka.grzegorz@gmail.com>
Reviewed-on: http://openocd.zylin.com/4106
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-05-31 08:16:17 +01:00
Palmer Dabbelt 51ab5a0c8b Return 5 (SIGBREAK) not 2 (SIGINT) after a step
GDB seems to just go off the rails if I return a SIGINT.
2017-05-25 18:31:58 -07:00
Palmer Dabbelt f0969e7c71 Pass EVENT_RESUMED in the RTOS
I missed this event.  It appears to do nothing.
2017-05-25 13:14:31 -07:00
Palmer Dabbelt ab77c5d792 Invalidate the register cache when rtos_hartid==-1
This means I don't know what hart to look at, so I might as well
invalidate the register cache.  Without this, you might get stale
registers the first time you ask for them.
2017-05-25 13:14:31 -07:00
Palmer Dabbelt faa6123e36 Invalidate the register cache on step, resume, reset
I thought OpenOCD did this, but it looks like that doesn't happen when
runningi in RTOS mode.  With this I can get to the end of most of the
RTOS tests, but they SIGINT instead of exiting.
2017-05-25 13:14:31 -07:00
Megan Wachs a1e07e58f4 Merge pull request #52 from riscv/v11_read_without_int
riscv-v11: Don't perform unexpected operation in cache_write
2017-05-25 10:51:27 -07:00
Megan Wachs e12f5575ef riscv-v11: Don't perform unexpected operation in cache_write 2017-05-22 22:02:01 -07:00
Palmer Dabbelt c431c0eb25 Check for abstractcs.busy, not just CMDERR_BUSY
This fixes a race condition when reading/writing memory.
2017-05-15 17:40:28 -07:00
Palmer Dabbelt a8cf04b839 Go back to 32-word read/write buffers
The larger buffers are really slow on Spike.
2017-05-15 16:57:25 -07:00
Palmer Dabbelt e31761df64 Don't re-read registers after they're written
This was just a sanity check.
2017-05-15 16:57:08 -07:00
Palmer Dabbelt 9d308db2bc Print out the actual CSR that's read 2017-05-15 16:56:50 -07:00
Palmer Dabbelt 8252b9d36c Build fixes 2017-05-15 13:39:58 -07:00