Bugfix the read side of flash protection:
- read the right register(s)!
- handle more than 64K
- record the results in the right places
- don't display garbage.
Partially bugfix the write side:
- use 2KB lock regions instead of 1KB pages (!)
- validate input range
- don't try to _remove_ protection (it's write-once)
- #define values we'll need to commit writes.
- ... still doesn't handle pages over 64KB mark, or commit writes
And minor cleanup and fixes:
- get rid of some forward decls
- properly locate a doxygen comment
- fix some bad indentation
- remove superfluous #include
- add a new part ID (many are still missing)
- make the downloaded algorithm code be read-only
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
These were all basically "can't happen" cases ... like having
state be corrupted by an alpha particle after the previous check
for whether a value was in-range.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Most of these happened to be in the target.h file.
Some of those are associated with symbols that could be
removed at some point ... e.g. NVP_ASSERT/true and its
sibling NVP_DEASSERT/false.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
The exception being declarations for drivers. Those should
be split out in some clean way -- like driver add/remove calls
made by initialization code -- but that's for another day.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
It's as if despite integers being 32-bits, GCC refuses to
convert a "uint32_t" to one of them.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Low latency low CPU processing power systems(embedded)
will benefit greatly from being able to inline certain
jtag_add_xxx() fn's. The trick is that this has to be
done in such a way as to allow implementing an OpenOCD
API with a shared library(eventually) on a PC hosted
OpenOCD.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Some versions of GCC don't understand that if you mask with 0x3
then have cases 0-3, it's not possible for a variable assigned in
all those branches to have no value at end-of-case. Feh.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
When starting up, say how many hardware breakpoints and watchpoints
are available on various targets.
This makes it easier to tell GDB how many of those resources exist.
Its remote protocol currently has no way to ask OpenOCD for that
information, so it must configured by hand (or not at all).
Update the docs to mention this; remove obsolete "don't do this" info.
Presentation of GDB setup information is still a mess, but at least
it calls out the three components that need setup.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Provide and use debug_reason_name() instead of expecting targets
to call Jim_Nvp_value2name_simple(). Less dependency on Jim, and
the code becomes more clear too.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Have various ARM cores delegate to arm_arch_state() to display
basic information, instead of duplicating that logic.
This shrinks the code, makes them all report when semihosting
is active, and highlights which data are specific to this core.
(Like ARM720 not having separate instruction and data caches.)
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Add a brief "setup with no customization" note showing the
how easily things can work if standard OpenOCD config scripts
already exist. We've had some new users comment that this
information is needlessly hard to find, so that starting to
use OpenOCD is more difficult than it should be.
Plus describe a few other issues that come up when setting
up an OpenOCD server.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Move most declarations in <target/armv4_5.h> to <target/arm.h>
and update users.
What's left in the older file is stuff that I think should be
removed ... the old register cache access stuff, which makes it
awkward to support microcontroller profile (Cortex-M) cores.
The armv4_5_run_algorithm() declaration was moved too, even
though it's not yet as generic as it probably ought to be.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Rename some (mostly) generic ARM functions:
armv4_5_arch_state() --> arm_arch_state()
armv4_5_get_gdb_reg_list() --> arm_get_gdb_reg_list()
armv4_5_init_arch_info() --> arm_init_arch_info()
Cores using the microcontroller profile may want a different
arch_state() routine though.
(Also fix strange indentation in arm_arch_state: use tabs only!
And update a call to it, removing assignment-in-conditional.)
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Move the ARM opcode macros from <target/armv4_5.h>, and a few
Thumb2 ones from <target/armv7m.h>, to more appropriate homes
in a new <target/arm_opcodes.h> file.
Removed duplicate opcodes from that v7m/Thumb2 set. Protected
a few macro argument references by adding missing parentheses.
Tightening up some of the line lengths turned up a curious artifact:
the macros for the Thumb opcodes are all 32 bits wide, not 16 bits.
There's currently no explanation for why it's done that way...
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Get rid of mrc_opcode() in favor of ARMV4_5_MRC() or, where
arm*20t should have used it, ARMV4_5_MCR() instead.
Basically, *writing* coprocessor registers shouldn't have
used the *read* opcode ... and both should stick to standard
opcode constructors, not rearranging parameter sequence any
more than already needed.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
The SRS and RFE instructions speed exception entry/exit by
making it easy to save and restore PC and SPSR. This handles
both ARM and Thumb2 encodings.
Fix minor PLD goofage; that "should never reach this point"
can't happen, so remove it.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
The low two bits are defined as should-be-zero-or-presereved.
We'll take the zero option, it's easier to enforce.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Behave like OMAP3530: force global software reset. Given the
patch to teach ARM11 how to use these events, and use VCR to
catch the reset vector, this works better than either the
current reset logic or than using SRST.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Rename the existing 'flash banks' implementation as 'flash list', and
replace the broken 'flash_banks' TCL wrapper with a new command handler.
Adds documentation for the new 'flash list' command in the user guide.
The 'flash banks' command produces a list that needs to be formatted
properly for GDB's 'mem info' to work properly. The flash_banks TCL
wrapper provided this formatting, but wrappers no longer work for
second-level commands as they did in the past. With this patch,
the 'flash_banks' command can be used with the new command syntax
and display the required information.
More updates from the code review by Steve Grubb <sgrubb@redhat.com>.
The Jim float-comparision bug just gets a comment not a fix, though.
Cc: Steve Grubb <sgrubb@redhat.com>.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Fall back to software breakpoint when vector catch isn't available.
Possible enhancements:
- add extra optional command parameter to select high vectors
- add extra optional command parameter to select hardware breakpoint
Signed-off-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Rename nand.h as flash/nand/core.h, chase consumers. The public APIs
need to be sorted out with imp.h, but this allows other changes to
begin improving the separation between policy and mechanism.
Moves #include <target/target.h> and #include "driver.h" into the
internal headers or source files, removing it from <flash/nand/core.h>.
Moves commands into nand/tcl.c and core implementation to 'nand/core.c'
and 'nand/fileio.c'. Eliminates 'flash/nand.c'.
Adds 'nand/imp.h' to share routines between TCL commands and core.
This work parallels the NOR directory, encapsulating the NAND drivers
into a separate file. This takes an extra step by encapsulating the
type of data structure used to manage the drivers, allowing it to be
changed from an array to a dynamic list in the future.
Remove an undesirable use of the CPSR symbol ... it needs to vanish.
Flag mode-to-number stuff as obsolete; say why ... should also vanish.
Get rid of no-longer-used mode and state typedefs.
Comment a few of the implicit ties to "classic ARM".
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
As with Cortex-A8, the WFAR register holds useful information
that should be recorded and, where relevant, displayed.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Tweak scanchain 7 debug messaging:
- show register addresses in decimal, matching ARM docs;
- remove some pointless noise
Avoid some needless roundtrips:
- skip SCAN_N when SCREG already holds that number (speeds up
polling and other common operations)
- avoid zeroing vcr twice on resume
Show the IR opcode as a label ("RESTART") too; and in decimal,
matching ARM docs.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
David Brownell
Spencer Oliver
Rafael Campos Las Heras
Øyvind Harboe
Zachary T Welch
Mathias Kuester
Nicolas Pitre