* Handle DMI busy in sba write.
If we encounter DMI busy on the NOP after a read, we'll never get the
value out because DMI busy is sticky. The read must be retried, but we
don't know whether it was ever issued. Since the read has side effects
(incrementing of the address) this retry must be handled at a higher
layer. So now dmi_op_timeout can be told to retry or not, and if retry
is disabled it'll return an error when busy.
Also actually properly do the retry in dmi_op_timeout(). Previously the
code would not reissue the command and end up returning a garbage value.
Change-Id: I3b52ebd51ebbbedd6e425676ac861b57fbe711b1
* Fix whitespace.
Change-Id: Icb76d964e681b22346368d224d1930c9342343f3
* Handle a few more DMI busy cases.
Change-Id: I8503a44e4bf935c0ebfff0d598fe4c322fda702a
* Explain when to use dmi_op_timeout(retry).
Change-Id: I1a5c6d76ac41a84472a8f79faecb2f48105191ff
* dmi_reset does not affect the current transaction.
That means the retry scheme we had been using works fine. This does
contain some minor tweaks, and now we pass my tests which hammer the DMI
busy case harder.
Change-Id: I13eee384dbba82bc5a5b1d387c75c547afe557b5
* Remove unnecessary changes to make the PR readable
Change-Id: I87079876e6965563cf590e3936b3595aeab8715d
* Move idle to end of line...
... because we go through run-test/idle after the scan.
Change-Id: I21a8cff22471f0b895d8cd8d25373dced9bf1ca9
* Remove unused code.
Change-Id: I07a7cdd2d64ca40a4fe181111a34cf55ff1928d1
The original OpenOCD code issued FENCE & FENCE.i twice for the current
hart (which is harmless, but takes time).
Avoiding this extra FENCE is a slight performance improvement. Per my rough
measurements, this improves performance of certain debugger actions
(single-stepping) by approx. 20% in single-hart systems.
* riscv: Fix bugs. Do not touch SATP if there is no MMU.
In some platform, there is no SATP register at all.
OpenOCD will report unexpected errors if SATP is unreadable.
So, use 'riscv_enable_virtual' to guard SATP access.
* riscv: fix format typo.
Abstract write size (aarsize) to shall always match the real
size of the register. This is because abstract write of smaller size
than the register need not be supported per spec (pg. 13 of RISC-V
External Debug Support ver. 0.13.2).
Fix memory access on 64-bit targets with no progbuf and sba that
supports 32-bit accesses but not 64-bit accesses. Bug was introduced in #419.
This fixes https://github.com/riscv/riscv-tests/issues/217.
Change-Id: Ib5ddf9886b77e3d58fe1d891b560ad03d5a46da1
When allocating scratch memory within RISC-V target
(scratch_reserve()), take into account whether progbuf
is writable or not, as determined by examine_progbuf().
* 64-bit progbuf memory reads work.
Change-Id: Ia3dbc0ee39a31ed0e5c38bbb3d9e089b2533f399
* 64-bit writes work.
Change-Id: Iae78711d715b6682817bb7cce366b0094bda8b23
* Let targets indicate number of supported data bits.
This is used by the default memory read/write functions when creating an
aligned block.
I'm adding this mainly to ensure I get coverage of the 64-bit progbuf
memory read/write code.
Change-Id: Ie5909fe537c9ec3360a8d2837f84be00a63de77b
* Make mingw32 happy.
Change-Id: Iade8c1fdfc72ccafc82f2f34923577032b668916
* WIP >16MB flashing.
Change-Id: Ibef9244f8573d2fbf19b80e5db7c2d3a10da59b5
* >16MB flashing works on Hi5 Unleashed
But now flashing HiFive1 is broken.
Change-Id: If939c9e21cf793ae727f3335205abd261a998c0c
* Fix off-by-one error on bank size.
Change-Id: I0e6e49db8c1bfddb2c5f67d40f62111246db8dcb
* Fix formatting.
Change-Id: I4211f9328c7d11ea659be9588a81aa2cd59017f9
* fix for batch scans not honoring presence of BSCAN tunnel
* fix formatting to placate checkpatch
* replace DIM with ARRAY_SIZE
* Refactor code that adds a bscan tunneled scan.
* Move bscan tunnel context to the batch structure, and in array
form, one per scan
* adjust code that was inconsistent with project code formatting standards
* 64-bit progbuf memory reads work.
Change-Id: Ia3dbc0ee39a31ed0e5c38bbb3d9e089b2533f399
* 64-bit writes work.
Change-Id: Iae78711d715b6682817bb7cce366b0094bda8b23
* Let targets indicate number of supported data bits.
This is used by the default memory read/write functions when creating an
aligned block.
I'm adding this mainly to ensure I get coverage of the 64-bit progbuf
memory read/write code.
Change-Id: Ie5909fe537c9ec3360a8d2837f84be00a63de77b
* Make mingw32 happy.
Change-Id: Iade8c1fdfc72ccafc82f2f34923577032b668916
This makes behavior when you've configured an SMP group of heterogeneous
targets a bit less weird. (You still shouldn't be doing that, since gdb
and who knows what else assumes that the targets in an SMP group are
homogeneous.)
Specifically, if you have a HiFive Unleashed board (where the first core
is fairly basic and the other 4 or more full-featured) this lets you
connect to all 5, and still have access to the FPU etc. on the higher
numbered cores.
Change-Id: I2e01f63f8753f78c29d7f414ea603e02bf0390e0
Also change the address that we use to link the PIC code, so that if
there is a PIC issue in the future it will show up on hardware I test
against.
Also remove fespi.S, which hasn't been used in a long time.
Change-Id: I667d930b48107a3522d619167c7afc335431b4b6
* Add riscv_batch_available_scans().
This function will query the number of available scans in a batch.
* Perform SBA writes with batch transactions for improved performance.
Using batch transactions avoids an unnecessary dmi read after every
dmi write, resulting in a significant performance improvement.
Fix expression "(pin_status | 0x4)" which was always true rather than
testing a bit. Untested - was clearly not expressing the intent of the
author by inspection. Found by automated tooling and rtrieu@google.com.
Signed-off-by: Seth LaForge <sethml@google.com>
Change-Id: I4bb91e60e8ce9757bf21976cc48de6f85a39c68d
Reviewed-on: http://openocd.zylin.com/5301
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
The C standard says that errno is set to ERANGE if an out-of-range value
is returned by strtol, strtoul, et. al., but it does not say that errno
is cleared if the function is successful (and, indeed, it is not on
glibc). This means that, if errno is ERANGE before strtol is called, and
if the value to be converted is exactly the maximum (or, for a signed
conversion, the minimum) legal value, COMMAND_PARSE_NUMBER will
erroneously indicate that the value is out of range.
Change-Id: I8a8b50a815b408a38235968f1c1d70297ea1a6aa
Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/5298
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
PAGE_SIZE is defined in system includes on some systems, this would
avoid the unintended conflict
Fixes
| src/flash/nor/esirisc_flash.c:95:9: error: 'PAGE_SIZE' macro redefined [-Werror,-Wmacro-redefined]
| #define PAGE_SIZE 4096
| ^
| /mnt/a/yoe/build/tmp/work/core2-64-yoe-linux-musl/openocd/0.10+gitrAUTOINC+7ee618692f-r0/recipe-sysroot/usr/inclu
de/limits.h:89:9: note: previous definition is here
| #define PAGE_SIZE PAGESIZE
Change-Id: I195b303fc88a7c848ca4e55fd6ba893796df55cc
Signed-off-by: Khem Raj <raj.khem@gmail.com>
Reviewed-on: http://openocd.zylin.com/5180
Tested-by: jenkins
Reviewed-by: Steven Stallion <sstallion@gmail.com>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
* Align algorithm stack to XLEN.
This fixes algorithm timeout on RV64 targets.
Also improve debug information in various places.
Change-Id: Id3121f9c6e753c6a7e14da511e4de0587a6f7b4d
* Compile 32-bit RISC-V algorithms for RV32E.
Change-Id: I33a698c0c6ba540de29fa0459242c72a67b0cbaa
* Remove debug code.
Change-Id: I37c966ce0f2d1fe68cd6ae0724d19ae95ebaf51b
* Dump start of gdb packets escaping non-printable.
Change-Id: Ie5f36b5c9041bfc0e5aa9543f0afe2c4810c2915
* Propagate flash programming errors.
Change-Id: I0c938ce7a1062bcc93426538cbc82424000f37b7
* Improve debug messaging.
Change-Id: I47ac3518f3b241986c677824864102936100adf6
* Add debug output to flash image.
This is helpful when you're debugging the flash algorithm itself, and a
nop when running it through OpenOCD.
Change-Id: Id44c6498c288872cc2cec79044116ac38198c572
* Make timeout depend on how much data is written.
Change-Id: I819efa04cd6f6bd6664afd5c53cc7a8a5c84f54e
* Fix issi erase commands.
This is required to flash HiFive Unleashed.
Change-Id: I33e4869d1d05ca8a1df6136bccf11afda61bfe10
* Fix running algorithm on multicore `-rtos riscv`.
The bug was that poll() might change the currently selected hart, and in
that case we'd access registers on that other hart after the algorithm
is finished.
Change-Id: I140431898285cf471b372139cef2378ab4879377
* Make fespi flash algorithm debugging optional.
Also add a scheme that allows you to see the stack trace of where a
failure occurred if debugging is enabled.
Change-Id: Ia9a3a9a941ceba0f8ff6b47da5a8643e5f84b252
There is no sense in displaying the max size (2M) as there is variants
of this device with reduced flash size
Change-Id: I40574064d75fdf2a038044c81038a6d7abc6c4dd
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5288
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Christopher Head <chead@zaber.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
SWM050 is a series of MCU product by Foshan Synwit Tech, which is
available in TSSOP-8 or SSOP-16 packages.
Adds flash driver for the internal 8KiB flash of the MCU. The registers
are based on reverse engineering the J-Flash blob provided by the
vendor.
Also adds a pre-made cfg file.
Change-Id: I0b29f0c0d062883542ee743e0750a4c6b6609ebd
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Caleb Szalacinski <contact@skiboy.net>
Reviewed-on: http://openocd.zylin.com/4927
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Added "exist=true" field to the reg_list struct to make access to the
dsp563xx registers again possible. Without it defaults to exist=false
and all the reg related functions will return nothing.
Fixes regression from b5964191f0
Change-Id: I9c256346735b8d66919c4ba83f528a8afca46ff9
Signed-off-by: Han Hartgers <han.hartgers@gmail.com>
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5239
Tested-by: jenkins
Fix two expressions where precedence of operator | vs ?: was clearly confused.
Untested - was clearly not expressing the intent of the author by inspection.
Found by automated tooling and rtrieu@google.com.
Change-Id: I46f190154797f8affc761caf3a15a1a9db53d702
Signed-off-by: Seth LaForge <sethml@google.com>
Reviewed-on: http://openocd.zylin.com/5281
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
1. Add get_thread_reg() to rtos. It's used in rtos_get_gdb_reg() to read
the value of a single register, instead of reading all register values
by calling get_thread_reg_list().
2. Add set_reg() to rtos. gdb_server uses this to change a single
register value for a specific thread.
3. Add target_get_gdb_reg_list_noread() so it's possible for gdb to get
a list of registers without attempting to read their contents.
The clang static checker doesn't find any new problems with this change.
Change-Id: I77f792d1238cb015b91527ca8cb99593ccc8870e
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: http://openocd.zylin.com/5114
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
* Clear cmderr by writing all ones.
This should have been part of #389.
Change-Id: Ie40e95fdd904af65c53d1f5de7c8464b27038ec0
* Don't update reg cache in register_write_direct().
This function explicitly bypasses any caches.
Change-Id: Ie3c9a1163e870f80c0ed75b74495079c527663e9
* Use only one hart to run algorithm.
Fixes a bug with `-rtos hwthread` where all harts would run when running
a flash/CRC algorithm, which would probably ruin flashing, and was
unexpectedly changing registers on other harts for the CRC algorithm.
Change-Id: Ia2f600624f4c8d4cab319861fef2c14722f08b53
* Adds support for RISCV Access Memory Abstract Commands
The Access Memory Abstract Command is one of the three optional
methods for reading and writing memory on a complient RISCV
debug module. The previous two options were already implemented
in OpenOCD.
Implementation Notes:
- aamvirtual is hard-coded to false until the design for accessing
virtual addresses is finalized.
- aamsizes corresponding to 8b, 16b, 32b, and 64b are supported.
128b support is postponed until it is required, as it will mean
changes to the read/write_abstract_arg() interface to pass 128b
values.
- aampostincrement is not used and hard-coded to false.
* Changes from review.
* Additional lint fixes and a typo from last commit.
* Fixing a clang error.
* Fixes a last-minute change that broke writes with width > 8b.
* Removing memcpy after adding read_from_buf().
Fake step is a hack introduced to make things work with real RTOSs that
have a concept of a current thread. The hwthread rtos always has access
to all threads, so doesn't need it.
This fixes a bug when running my MulticoreRegTest against HiFive
Unleashed where OpenOCD would return the registers of the wrong thread
after gdb stepped a hart.
Change-Id: I64f538a133fb078c05a0c6b8121388b0b9d7f1b8
This is causing repeated build failures. Its design is so fundamentally
broken that if someone actually wants to use it, a full rewrite is the
only option. So it's not even worth deprecating in the hope that someone
will notice and fix it, just get rid of it.
Change-Id: I513069919a3873bd69253110f7fb6f622ee7d061
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/5243
Tested-by: jenkins
Reviewed-by: Jeffrey Booher-Kaeding <Jeff.Booher-Kaeding@arm.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tim Newsome
Jan Matyas
Hsiangkai
Hsiangkai
bluew
Greg Savin
darius-bluespec
Seth LaForge
Christopher Head
Marc Schink
Khem Raj
Tarek BOCHKATI
Caleb Szalacinski
Han Hartgers
dave-estes-syzexion
Andreas Fritiofson