Config for Intel's "Lubbock" PXA255 development board. Even more
so than the PXA255 itself, this is obsolete. AFAIK this was the
first generally available development platform for PXA255. Intel
stopped providing these after other devel boards became available.
One interesting thing about this board from the OpenOCD perspective
is probably its flash configuration. Each bank is 32 bits wide,
built from two 16-bit StrataFlash chips wired in parallel. This
doubles throughput ... it reads/writes 32 bits in the time a single
chip takes to write just 16 bits.
This conf mostly works, given XScale bugfixes, but has some issues
(notably: no access to the on-board SDRAM) flagged by FIXMEs.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
We currently do something unusual: version codes in config.in get
updated after the release, which means that "git describe" won't
match up to development version labels. Comment that trouble spot.
We can fix this by switching away from the major/minor/micro type
release numbering, as various other projects have done. The major
numbers basically don't tend to change, and doing a good job with
micro versions is so annoying that they rarely change either.
Contrast releases to git snapshot tarballs. Mention that
releases have some quality-improvement focus, with special
non-"dev" version IDs. Explain more about version IDs,
using "openocd -v" to see them, etc;
Make release milestone info be less specific about timing,
and presume we have both a merge window and an RC stage.
Rework the release process information to match reality a
bit more closely. Reference the version.sh script (in one
place the wrong script was referenced). Bugfix branches
get special treatment, while non-bugfix releases are more
or less what *defines* being the mainline branch.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
The "source" command isn't accepted by ASH; easy to fix.
Failures with "-e" are harder to fix. Remove the "-e"
(for now) and force bash, for safety.
Un-obfuscate the release steps, by using names instead
of numbers. Comment the version-number manipulation.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Various include files require some other include files
to be included first. Copied solution from net/if.h.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
To support breakpoints, flush data cache line and invalidate
instruction cache when 4 and 2 byte words are written.
The previous code was trying to write directly to the physical
memory, which was buggy and had a number of other situations
that were not handled.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Fixed bug: if virtual address for working memory was not specified
and MMU was enabled, then address 0 would be used.
Require working address to be specified for both MMU enabled
and disabled case.
For some completely inexplicable reason this fixes the regression
in svn 2646 for flash write in arm926ejs target. The logs showed
that MMU was disabled in the case below:
https://lists.berlios.de/pipermail/openocd-development/2009-November/011882.html
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
This change is necessary to debug AT91SAM9260 on my PC with a
FT2232H dongle.
Signed-off-by: Dimitar Dimitrov <dinuxbg@gmail.com>
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Mention the autoprobing as a tool that may be useful when
figuring out how to set up; and add a section showing how
to use that mechanism (with an example).
Strengthen the differences between config and run stage
descriptions; add a section for the latter.
Mention Dragonite.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
For some reason, all the interals are documented by default.
This is wrong for two basic reasons:
- We need to focus on public interfaces, since those are
the architectural interfaces and relationships.
- Since virtually nothing has doxygen support yet, this
maximizes the noise, and minimizes the usefulness of
doxygen output.
So don't expose so much by default.
Gets rid of the runtime warning "stm32.bs: nonstandard IR mask"
[dbrownell@users.sourceforge.net: line lengths, note issue, section ref]
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Just use the array of names we're given, ignoring indices.
The "reserved means don't use" patch missed that change.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
This gets rid of runtime warnings from the use of numbers.
STM32 and LPC2103 were tested. Other LPC updates are the
same, and so are safe. The CFI updates match other tested
changes now in the tree.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
There were a few more changes worth mentioning, including support
for more JTAG adapters, boundary scan improvements, another NAND
driver, and the Win64 stuff.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
I'm suspecting this code can never have worked, since the
original commit (svn #335) in early 2008.
Fix is just copy/paste from another (working) function.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Add interface configs for two new high speed JTAG
adapters from Olimex. They need some other speed
related tweaks to work well at high speed.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Implement XSVF support for detailed state path transitions,
by collecting sequences of XSTATE transitions into paths
and then calling pathmove().
It seems that the Xilinx tools want to force state-by-state
transitions instead of relying on the standardized SVF paths.
Like maybe there are XSVF tools not implementing SVF paths,
which are all that we support using svf_statemove().
So from IRPAUSE, instead of just issuing "XSTATE DRPAUSE"
they will issue XSTATES for each intermediate state: first
IREXIT2, then IRUPDATE, DRSELECT, DRCAPTURE, DREXIT1, and
finally DRPAUSE. This works now.
Handling of paths that go *through* reset is a trifle dodgey,
but it should be safe.
Tested-by: Wookey <wookey@wookware.org>
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Unneeded exports cause confusion about the module interfaces.
Make most functions static, and fix some line-too-long issues.
Delete some now-obviously-unused code.
The forward decls are just code clutter; move their references
later, after the normal declarations. (Or vice versa.)
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Unneeded exports cause confusion about the module interfaces.
Only the Feroceon code builds on this, so only routines it
reuses should be public.. Make most remaining functions
static, and fix some of the line-too-long issues.
The forward decls are just code clutter; move their references
later, after the normal declarations. Turns out we don't need
even one forward declaration in this file.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
The Hex parser uses a fixed number of sections. When the
number of sections in the file is greater than that, the
stack get corrupted and a CHECKSUM ERROR is detected
which is very confusing.
This checks the number of sections read, and increases
IMAGE_MAX_SECTIONS so it works on my file.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Update documentation to reflect GIT methodology. Rewrite release.sh
script to use appropriate process. With this update, tools/release.sh
can be used for producing private release tags on local branches.
The documentation still needs work, but their use for v0.3.x should
help rectify the deficiences.
A '.*' rule prevents the 'git submodule add' from correctly adding the
first submodule, because it creates the .gitmodule file. This file will
not be added (without -f) result in incomplete submodule commits.
The new rules mask the specific files present in my own build tree, but
additional rules may be needed to hide other types of temporary files.
Only type 1 branch instruction has a condition code, not type 2.
Currently they're both tagged with ARM_B which doesn't allow for the
distinction.
Signed-off-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
A Thumb BLX instruction is branching to ARM code, and therefore the
first 2 bits of the target address must be cleared.
Signed-off-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
This patch includes partial support for these new JTAG adapters.
More complete support will require updates to the libftdi code,
for EEPROM access.
[dbrownell@users.sourceforge.net: fix whitespace, linelen, etc ]
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Currently, OpenOCD is always caching the PC value without the T bit.
This means that assignment to the PC register must clear that bit and set
the processor state to Thumb when it is set. And when the PC register
value is transferred to another register or stored into memory then
the T bit must be restored.
Discussion: It is arguable if OpenOCd should have preserved the original
PC value which would have greatly simplified this code. The processor
state could then be obtained simply by getting at bit 0 of the PC. This
however would require special handling elsewhere instead since the T bit
is not always relevant (like when PC is used with ALU insns or as an index
with some addressing modes). It is unclear which way would be simpler in
the end.
Signed-off-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Whenever an unconditional branch with the H bits set to 0b10 is met, the
offset must be combined with the offset from the following opcode and not
ignored like it is now.
A comment in evaluate_b_bl_blx_thumb() suggests that the Thumb2 decoder
would be a simpler solution. That might be true when single-stepping of
Thumb2 code is implemented. But for now this appears to be the simplest
solution to fix Thumb1 support.
Signed-off-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Calling it first with every opcodes and then testing if the opcode
was indeed a branch instruction is wasteful and rather strange.
If ever thumb_pass_branch_condition() has side effects (say, like
printing a debugging traces) then the result would be garbage for most
Thumb instructions which have no condition code.
While at it, let's make the nearby code more readable by reducing some of
the redundant brace noise and reworking the error handling construct.
Signed-off-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Now I can issue "reset halt" and have everything act smoothly;
the vector_catch hardware is obviously not kicking in, but the
rest of the reset sequence acts sanely.
- TAP "setup" event enables the DAP, not omap3_dbginit
(resolving a chicken/egg bug I noted a while back)
- Remove stuff from omap3_dbginit which should never be
used in event handlers
- Cope better with slow clocking during reset
Also, stop hard-wiring the target name: use the input params in
the standard way, and set up $_TARGETNAME as an output param.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Krzysztof Kajstura
David Brownell
Øyvind Harboe
Dimitar Dimitrov
Freddie Chopin
Spencer Oliver
Michael Roth
Zachary T Welch
Franck HÉRÉSON
Nicolas Pitre
Oleg Seiljus