Commit Graph

4027 Commits (27401e4c80b137f599954ac521387b247002770c)

Author SHA1 Message Date
Øyvind Harboe 27401e4c80 zy1000: arm11 load is now faster
290kBytes/s @ 8MHz, no need to inline jtag_tap_next_enabled().

Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
2010-03-01 15:27:12 +01:00
Øyvind Harboe afbf927663 zy1000: add jtag_add_tms_seq support
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
2010-03-01 13:36:03 +01:00
Øyvind Harboe 761d4555b8 jtag: the post TAP state is now passed to the drivers
after clocking out a tms sequence, then the TAP will be
in some state. This state is now handed to the drivers.

TAP_INVALID is a possible state after a TMS sequence if
switching to SWD.

Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
2010-03-01 08:30:29 +01:00
Spencer Oliver 409e23e39b armv4_5: remove core_type check in mcr/mrc cmd
core_type check is not required as the core function will be
null for cores that do not support the mcr/mrc functions.

Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
2010-02-28 23:06:49 +00:00
Spencer Oliver 57fc63f9f1 cm3-ftest: change to use arm disassemble
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
2010-02-28 22:52:06 +00:00
Spencer Oliver c9560ba190 stellaris: recover_command use usleep rather than sleep
windows api does not define a posix sleep, use usleep that
has an openocd wrapper to the win32 native function.

Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
2010-02-28 22:48:57 +00:00
Spencer Oliver 73c1cff7c2 FT2232: add missing enum when using ftd2xx library
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
2010-02-28 22:48:51 +00:00
Spencer Oliver 8d13a46626 semihosting: add armv7m semihosting support
do_semihosting and arm_semihosting now check the core type and
use the generic arm structure.

Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
2010-02-28 22:48:44 +00:00
Spencer Oliver 9d6ede25dd semihosting: move semihosting cmd to arm cmd group
Move semihosting cmd to the arm cmd group.

Targets that support semihosting will setup the
setup_semihosting callback function.

Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
2010-02-28 22:48:37 +00:00
Spencer Oliver 550abe7396 CortexM3: move disassemble cmd to arm cmd group
Rather than using a Cortex disassemble cmd, we now use
the arm generic version.

Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
2010-02-28 22:48:19 +00:00
Spencer Oliver 4c9f29bd9c ARMv7M: add arm cmd group
- Add arm cmd group to armv7m cmd chain.
 - arm cmd's now check the core type before running a cmd.
 - todo: add support for armv7m registers for reg cmd.

Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
2010-02-28 22:47:51 +00:00
Spencer Oliver b8d8953ae9 MIPS: add mips algorithm support
- add mips support for target algorithms.
 - added handlers for target_checksum_memory and target_blank_check_memory.
 - clean up long lines

Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
2010-02-28 22:26:53 +00:00
Spencer Oliver a851ce0d6f ARMv7M: use software breakpoints for algorithms
- armv7m_run_algorithm now requires all algorithms to use
   a software breakpoint at their exit address
 - updated all algorithms to support this

Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
2010-02-28 22:26:52 +00:00
Mariano Alvira 0324eb2496 Add board/redbee-usb.cfg
The Redbee USB is a small form-factor usb stick from Redwire, LLC
(www.redwirellc.com/store), built around a Freescale MC13224V
ARM7TDMI + 802.15.4 radio (plus antenna).

It includes an FT2232H for debugging, with Channel B connected to the
mc13224v's JTAG interface (unusual) and Channel A connected to UART1.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-02-28 10:33:46 -08:00
Mariano Alvira 63763345d9 add board/redbee-econotag.cfg and JTAG support
The Redbee Econotag is an open hardware development kit from
Redwire, LLC (www.redwirellc.com/store), for the Freescale
MC13224V ARM7TDMI + 802.15.4 radio.

It includes both an MC13224V and an FT2232H (for JTAG and UART
support).  It has flexible power supply options.

Additional features are:

  - inverted-F pcb antenna
  - 36 GPIO brought out to 0.1" pin header
    (includes all peripheral pins)
  - Reset button
  - Two push buttons (on kbi1-5 and kbi0-4)
  - USB-A connector, powered from USB
  - up to 16V external input
  - pads for optional buck inductor
  - pads for optional 32.768kHz crystal
  - 2x LEDS on TX_ON and RX_ON

[ dbrownell@users.sourceforge.net: shrink lines; texi ]

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-02-27 22:52:34 -08:00
Mariano Alvira e4a40d257d Add target/mc13224v.cfg
The MC13224V is a FreeScale ARM7TDMI based IEEE802.15.4 platform for
Zigbee and similar low-power wireless applications. Using PIP
(Platform In Package) technology, it integrates: an RF balun and
matching network; a buck converter (only an external inductor is
necessary); 96KB of SRAM; and 128KB of non-volatile memory.

It has an integrated bootloader and can boot from a variety of sources:
external SPI or I2C non-volatile memory, an image loaded over UART1,
or the internal non-volatile memory. The image loaded from one of these
sources is executed directly from SRAM starting at location 0x00400000.

Open source development code at http://mc1322x.devl.org

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-02-27 22:51:41 -08:00
David Brownell e70d42a727 new "stellaris recover" command
Stellaris chips have a procedure for restoring the chip to
what's effectively the "as-manufactured" state, with all the
non-volatile memory erased.  That includes all flash memory,
plus things like the flash protection bits and various control
words which can for example disable debugger access.  clearly,
this can be useful during development.

Luminary/TI provides an MS-Windows utility to perform this
procedure along with its Stellaris developer kits.  Now OpenOCD
users will no longer need to use that MS-Windows utility.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-02-27 00:31:35 -08:00
David Brownell 3ef9beb52c ADIv5 DAP ops switching to JTAG or SWD modes
Define two new DAP operations which use the new jtag_add_tms_seq()
calls to put the DAP's transport into either SWD or JTAG mode, when
the hardware allows.

Tested with the Stellaris 'Recovering a "Locked" Device' procedure,
which loops five times over both of these.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-02-27 00:31:35 -08:00
David Brownell 8c9b52e8b6 ft2232: implement TMS sequence command
Implement the new TMS_SEQ command on FT2232 hardware.
Also, swap a bogus exit() call with a clean failure return.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-02-27 00:12:38 -08:00
David Brownell a3245bd7cd interface: define TMS sequence command
For support of SWD we need to be able to clock out special bit
sequences over TMS or SWDIO.  Create this as a generic operation,
not yet called by anything, which is split as usual into:

 - upper level abstraction ... here, jtag_add_tms_seq();
 - midlayer implementation logic hooking that to the lowlevel code;
 - lowlevel minidriver operation ... here, interface_add_tms_seq();
 - message type for request queue, here JTAG_TMS.

This is done slightly differently than other operations: there's a flag
saying whether the interface driver supports this request.  (In fact a
flag *word* so upper layers can learn about other capabilities too ...
for example, supporting SWD operations.)

That approach (flag) lets this method *eventually* be used to eliminate
pathmove() and statemove() support from most adapter drivers, by moving
all that logic into the mid-layer and increasing uniformity between the
various drivers.  (Which will in turn reduce subtle bugginess.)

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-02-27 00:12:38 -08:00
Mariano Alvira 4a64820f23 ft2232: add a mechanism to specify channel in layout structs
FT2232-family chips have two or more MPSSE modules.   FTDI documentation
calls these channels.  JTAG adapter drivers thus need to be able to choose
which channel to use.  (For example, one channel may connect to a board's
microcontroller, while another connects to a CPLD.)

Since each channel has its own USB interface, libftdi (somewhat confusingly)
identifies channels using INTERFACE_* symbols.  Most boards use INTERFACE_A
for JTAG, which is the default in OpenOCD.  But some wire up a different one.

Note that there are two facets of what makes a wiring "layout":

 - The mapping between debug signals map and channel signals ... embedded
   in C functions.

 - Label used in Tcl configuration scripts ... part of the "layout" structure.

By letting the channel be part of the layout struct, we permit sharing the C
functions between Tcl-visible layouts, when those signal mappings are reused.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-02-25 00:01:55 -08:00
David Brownell 79010bf3df ARM ADIv5 doxygen and cleanup
Add doxygen for mem_ap_read_buf_u{8,16,32}() calls,
and shrink a few overlong lines.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-02-24 23:46:46 -08:00
Hans Peter Mortensn 7abe9f38b2 AVR flash: handle AT90CAN128 chips
I have successfully programmed the AT90CAN128, based on the mega128  
with some small modifications.

[ dbrownell@users.sourceforge.net: patch cleanup ]

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-02-24 23:35:12 -08:00
David Brownell 75067c4042 ARM ADIv5: rename more JTAG-specific routines
Highlight more of the internal JTAG-specific utilities, so it's
easier to identify code needing changes to become transport-neutral.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-02-23 23:36:42 -08:00
Øyvind Harboe faef631a4d arm11: improve performance using minidriver hook
zy1000 performance for GDB load went from 100kBytes/s
to 300kBytes/s @ 8 MHz by implementing the inner loop
of unack arm11 memory writes directly on top of the hw
fifo.

Profiling info:

 78.57      0.77     0.77                             arm11_run_instr_data_to_core_noack_inner
  5.10      0.82     0.05                             memcpy
  4.08      0.86     0.04                             jtag_tap_next_enabled
  3.06      0.89     0.03                             gdb_input

Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
2010-02-22 10:15:51 +01:00
Øyvind Harboe 1f5883ea56 arm11: allow minidrivers to implement inner loop of memory writes
This allows minidrivers to e.g. hardware accelerate memory
writes.

Same trick as is used for arm7/9 dcc writes.

Added error propagation for memory transfer failures in
code rearrangement.

Also the JTAG end state is not updated until after
the memory write run is complete.

Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
2010-02-22 10:15:51 +01:00
Øyvind Harboe 90efc404f3 zy1000: jtag_add_dr_scan() performance improvement
Reduce overhead in jtag_add_dr_scan() a bit.

Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
2010-02-22 08:00:10 +01:00
David Brownell c21c740a89 ft2232 table init cleanup
Use labeled initializers in the table of layouts instead of
positional ones.  This ls cleaner and less error prone, plus
it simplifies patches which add members to these structure.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-02-21 17:19:08 -08:00
David Brownell dc342f45f6 Developer's Guide: refresh release procedures
Be a closer match to what I've actually done for the past few cycles.

In particular, hold off pushing repository updates until after the
packages are published, as part of opening the merge window, and
mention the utility commands which actually create the archives.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-02-21 16:55:17 -08:00
David Brownell c8ea748dc2 ADIv5: relocate memacess_tck cycles
When using an AP to access a memory (or a memory-mapped register),
some extra TCK (assuming JTAG) cycles should be added to ensure
the AP has enugh time to complete that access before trying to
collect the response.

The previous code was adding these cycles *before* trying to
access (read or write) data to that address, not *after*.  Fix
by putting the delays in the right location.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-02-21 14:58:16 -08:00
David Brownell 3b68a708c2 ADIv5: remove ATOMIC/COMPOSITE interface mode
This removes context-sensitivity from the programming interface and makes
it possible to know what a block of code does without needing to know the
previous history (specifically, the DAP's "trans_mode" setting).

The mode was only set to ATOMIC briefly after DAP initialization, making
this patch be primarily cleanup; almost everything depends on COMPOSITE.
The transactions which shouldn't have been queued were already properly
flushing the queue.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-02-21 14:56:56 -08:00
David Brownell ecff73043c ARM: ADIv5, deadcode cleanup
I have no idea what the scan_inout_check() was *expecting* to achieve by
issuing a read of the DP_RDBUFF register.  But in any case, that code was
clearly never being called ("invalue" always NULL) ... so remove it, and
the associated comment.

Also rename it as ap_write_check(), facilitating a cleanup of its single
call site by removing constant parameters.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-02-21 14:54:54 -08:00
David Brownell 39cfe62796 ARM: ADIv5 code shrinkage, cleanup
adi_jtag_dp_scan_u32() now wraps adi_jtag_dp_scan(), removing
code duplication.  Include doxygen for the former.  Comment
some particularly relevant points.  Minor fault handling fixes
for both routines:  don't register a callback that can't run,
or return ERROR_OK after an error.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-02-21 14:53:15 -08:00
David Brownell a97bb67543 ADIv5 clean up AP fault handling
Pass up fault codes from various routines, so their callers
can clean up after failures, and remove the FIXME comments
highlighting those previously goofy code paths.

 dap_ap_{read,write}_reg_u32()
 dap_ap_write_reg()
 mem_ap_{read,write}_u32()
 mem_ap_{read,write}_atomic_u32()
 dap_setup_accessport()

Make dap_ap_write_reg_u32() just wrap dap_ap_write_reg(),
instead of cloning its core code (and broken fault handling).

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-02-21 14:51:19 -08:00
David Brownell 249263d29d ADIv5 clean up AP selection and register caching
Handling of AP (and AP register bank) selection, and cached AP
registers, is pretty loose ... start tightening it:

 - It's "AP bank" select support ... there are no DP banks.  Rename.
   + dap_dp_bankselect() becomes dap_ap_bankselect()
   + "dp_select_value" struct field becomes "ap_bank_value"

 - Remove duplicate AP cache init paths ... only use dap_ap_select(),
 and don't make Cortex (A8 or M3) cores roll their own code.

 - For dap_ap_bankselect(), pass up any fault code from writing
 the SELECT register.  (Nothing yet checks those codes.)

 - Add various bits of Doxygen

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-02-21 14:48:04 -08:00
David Brownell 1aac72d243 ARM: keep a handle to the PC
Keep a handle to the PC in "struct arm", and use it.
This register is used a fair amount, so this is a net
minor code shrink (other than some line length fixes),
but mostly it's to make things more readable.

For XScale, fix a dodgy sequence while stepping.  It
was initializing a variable to a non-NULL value, then
updating it to handle the step-over-active-breakpoint
case, and then later testing for non-NULL to see if
it should reverse that step-over-active logic.  It
should have done like ARM7/ARM9 does: init to NULL.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-02-21 14:34:33 -08:00
David Brownell a299371a9e ARM DPM: support adding/removing HW breakpoints
Generalize the core of watchpoint setup so that it can handle
breakpoints too.  Create breakpoint add/remove routines which
will use that, and hook them up to target types which don't
provide their own breakpoint support (nothing, yet).

This suffices for hardware-only breakpoint support.  The ARM11
code will be able to switch over to this without much trouble,
since it doesn't yet handle software breakpoints.  Switching
Cortex-A8 will be a bit more involved.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-02-21 14:32:34 -08:00
David Brownell 27c068c1f8 ARM11: per-core options should not be global
Address some FIXME comments by getting rid of globals, moving
per-core parameters in the existing per-core data structure.

This will matter most whenever there are multiple ARM11 cores,
e.g. ARM11 MPcore chips, but in general is just cleanup.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-02-21 14:30:27 -08:00
David Brownell ce1feaa732 ARMv7-M: start using "struct arm"
This sets up a few of the core "struct arm" data structures so they
can be used with ARMv7-M cores.  Specifically, it:

 - defines new ARM core_modes to match the microcontroller modes
   (e.g. HANDLER not IRQ, and two types of thread mode);

 - Establishes a new microcontroller "core_type", which can be
   used to make sure v7-M (and v6-M) cores are handled right;

 - adds "struct arm" to "struct armv7m" and arranges for the
   target_to_armv7m() converter to use it;

 - sets up the arm.core_cache and arm.cpsr values

 - makes the Cortex-M3 code maintain arm.map and arm.core_mode.

This is currently set up as a parallel data structure, primarily to
minimize special cases for the semihosting support with microcontroller
profile cores.

Later patches can rip out the duplicative ARMv7-M support and start
reusing core ARM code.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-02-21 14:28:53 -08:00
David Brownell b853b9dbc0 Open the merge window for the 0.5.0 release cycle.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-02-21 13:27:37 -08:00
David Brownell 56e74908d1 Label builds as OpenOCD v0.4.0
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-02-21 12:20:13 -08:00
David Brownell 4aa0a4d811 User's Guide mentions OS-specific installation
Specifically the Linux issue of needing "udev" rules, and MS-Windows
needing driver configuration.

Also, update the existing udev note to use the correct name of that
rules file in the source tree.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-02-21 09:29:24 -08:00
David Brownell bb4cb7935e arm920t line length cleanup
The recent patch to fixbreakpoints and dcache handling added
a bunch of overlong lines (80+ chars) ... shrink them, and do
the same to a few lines which were already overlong.

Also add a few FIXME comments to nudge (a) replacement of some
magic numbers with opcode macros, which will be much better at
showing what's actually going on, and (b) correct return codes.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-02-20 20:47:38 -08:00
David Brownell 57d5673dea CSB337 board cleanup (quasi-regression)
Get rid of new nasty warning:

NOTE! Severe performance degradation without fast memory access enabled...

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-02-20 20:47:38 -08:00
David Brownell d2a2c14d20 FreeBSD buildfix
Fix an unused variable warning seen when building the parport driver
under FreeBSD.

Using information from Xiaofan Chen <xiaofanc@gmail.com>

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-02-20 11:11:43 -08:00
Marc Pignat 3f30563c88 atm920t : fix breakpoints and data cache handling
Breakpoints did not work because the data cache was not flushed
properly.

As a bonus add capability to write to memory marked as read only
by the MMU, which allows software breakpoints in such memory
regions.
2010-02-19 08:18:12 +01:00
David Brownell aa8db989b9 ARM920T scanchain 15 comments/cleanup
For folk who don't know the ARM920 JTAG interface very well, the
two modes of scan chain 15 access to CP15 are confusing.

Make those parts of the ARM920 code less opaque, by:

 - Adding comments referencing the relevant parts of the TRM,
   catching up to similar updates in the User's Guide.

 - Replacing magic numbers in physical access clients with
   symbolic equivalents.

No functional change.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-02-16 18:50:16 -08:00
Øyvind Harboe fa1cfc2d4d gpl: fix GPL startup message
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
2010-02-15 22:59:41 +01:00
David Brownell 5869992314 LPC1768.cfg -- partial fixes for bogus reset-init handler
Cortex-M targets don't support ARM instructions.

Leave the NVIC.VTOR setup alone, but comment how the whole
routine looks like one big bug...

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-02-15 13:39:16 -08:00
Mathias Kuester 52d4ba3467 fix crash with DSP563XX
When a DSP563xx-aware GDB asks OpenOCD for target registers,
the result should be a GDB with register data ... not an
OpenOCD crash.

(Note that mainline GDB doesn't currently support this core,
so for now, this requires a GDB with FreeScale patches.)

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-02-14 12:59:10 -08:00