The schematics used for writing the config file were incorrect, real
hardware needs ACBUS3 _low_ as it's connected directly to the output
buffer's !OE pin.
Also apparently sometimes TUMPA comes with default FTDI IDs.
Real-life tested (including TRST and SRST) with a custom stm32f103
board, thanks to Mike Wang for the adapter sample.
Change-Id: Iab566e6d14f8392030f6ff2c8d976e1b57cf5ce6
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/1789
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This is a tcl implementation of public domain tests by Michael Barr,
http://www.barrgroup.com/Embedded-Systems/How-To/Memory-Test-Suite-C
The initial porting is done by Shane Volpe and posted to the mailing
list:
http://www.mail-archive.com/openocd-development@lists.berlios.de/msg16676.html
This patch includes some cosmetic amendments plus hardcodes 32bit word
size (as the code depends on memread32/memwrite32 anyway) which fixes
original code's issue of testing only the first quarter of the
specified nBytes.
Change-Id: I5f3a66f1f16fc4082c7a5a6aba338430646ed21c
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/1455
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-by: Mathias Küster <kesmtp@freenet.de>
Some boards might have RCLK omitted from the JTAG connector and if the
interface claims support for it, OpenOCD will end up trying to use
RCLK while it's actually impossible.
This is a "cd tcl/target; sed -i s/jtag_rclk/adapter_khz/g *" patch.
Change-Id: Iee7337107bc1457966b104389ba9db75a9c860b4
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/1695
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-by: Mathias Küster <kesmtp@freenet.de>
Initial support for using the jtag interface to the Marvell Armada 370
family of SoCs.
Change-Id: Id823a567e8805ac622c3c330bc111297c1dae37e
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Reviewed-on: http://openocd.zylin.com/1690
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Almost the same as the LM4F120 LaunchPad but the chip is using the new
naming scheme (Tiva C series), supports USB OTG and has some new PWM
hardware blocks.
Change-Id: I6a7b2df76768766471f366cddaf64df3cc63f5f2
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/1647
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Add support for OpenRISC target. This implementation
supports the adv_debug_sys debug unit core. The mohor
dbg_if is not supported. Support for mohor TAP core
and Altera Virtual JTAG core are also provided.
Change-Id: I3b1cfab1bbb28e497c4fca6ed1bd3a4362609b72
Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
Reviewed-on: http://openocd.zylin.com/1547
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
This patch adds a driver for the jtag_vpi server [1]. This server is
now part of the ORPSoC version 3 (OpenRISC Reference Platform SoC).
The jtag_vpi server provides an interface between OpenOCD and a simulated
core.
[1] http://github.com/fjullien/jtag_vpi
Change-Id: I717b72cace4845f66c878581345074f99002e21a
Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
Reviewed-on: http://openocd.zylin.com/1609
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
The smallest available RAM size for this family is 2K, set this as the
default. Issue reported by quitte on IRC.
Change-Id: I3318f7f268f7681ffe2cddab61820f4b94c4e5fd
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1559
Tested-by: jenkins
Added new configuration file for gw16042 device.
Also added this to interface/ftdi examples in documentation.
Change-Id: I07bb10bfc79a5d13007288cd57f254d889075214
Signed-off-by: Pushpal Sidhu <psidhu@gateworks.com>
Reviewed-on: http://openocd.zylin.com/1563
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
The end users on IRC report that actual USB device has different
information in its descriptor so it doesn't match. Remove it
altogether.
Change-Id: Id7841667390a514581e630e67b9283675803135b
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/1548
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This commit adds two tcl configuration files, one for the Altera
Cyclone V SoC series, and one for the SoCkit development board.
The board configuration is able to halt and resume the cpu cores,
and dump register contents etc. It has not been fully tested, however.
Change-Id: Id3f18c3408975cf986a5f5aec410b5b13240c35e
Signed-off-by: Brad Riensche <brad.riensche@gmail.com>
Reviewed-on: http://openocd.zylin.com/1494
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This adds example config and flash driver for russian Cortex-M3
microcontroller model.
Run-time tested on MDR32F9Q2I evaluation board; the flash driver
should be compatible with MDR32F2x (Cortex-M0) too but I lack hardware
to test.
There're no status bits at all, the datasheets specifies some delays
for flash operations instead. All being in <100us range, they're hard
to violate with JTAG, I hope. There're also no flash identification
registers so the flash size and type has to be hardcoded into the
config.
The flashing is considerably complicated because the flash is split
into pages, and each page consists of 4 interleaved non-consecutive
"sectors" (on MDR32F9 only, MDR32F2 is single-sectored), so the
fastest way is to latch the page and sector address and then write
only the part that should go into the current page and current sector.
Performance testing results with adapter_khz 1000 and the chip running
on its default HSI 8MHz oscillator:
When working area is specified, a target helper algorithm is used:
wrote 131072 bytes from file testfile.bin in 3.698427s (34.609 KiB/s)
This can theoretically be sped up by ~1.4 times if the helper
algorithm is fed some kind of "loader instructions stream" to allow
sector-by-sector writing.
Pure JTAG implementation (when target memory area is not available)
flashes all the 128k memory in 49.5s.
Flashing "info" memory region is also implemented, but due to the
overlapping memory addresses (resulting in incorrect memory map
calculations for GDB) it can't be used at the same time, so OpenOCD
needs to be started this way: -c "set IMEMORY true" -f
target/mdr32f9q2i.cfg
It also can't be read/verified because it's not memory-mapped anywhere
ever, and OpenOCD NOR framework doesn't really allow to provide a
custom handler that would be used when verifying.
Change-Id: I80c0632da686d49856fdbf9e05d908846dd44316
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/1532
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Austriancoder on IRC reports getting this ID on his board.
Change-Id: Ie859f0ee422e18fdb94bf817cdd2b41d15b968da
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/1533
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Add support for DENX M53EVK board and it's integrated on-board
JTAG adapter using FT2232H.
Change-Id: I022dcafa7799bb84a7873ba67ed82f1e49094320
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-on: http://openocd.zylin.com/1461
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Pull the jtag_rtck setting from imx51.cfg and imx53.cfg . Since
not all boards using these CPUs do support RTCK signal, move the
configuration of RTCK into board files.
Change-Id: I632c5d38e00ada8779a451cd26428fd122452001
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-on: http://openocd.zylin.com/1460
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
It pointed to the Flyswatter 1 page.
Change-Id: Ib7e82669a31cad2bf8f6ba4a60b25ef9920b2584
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/1478
Tested-by: jenkins
Reviewed-by: Xiaofan <xiaofanc@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Ignore version of Boundary Scan TAP in newer revisions of the str9.
Change-Id: I6e205f8c731f07078c469e686025857c180f3a6d
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1436
Tested-by: jenkins
Add a config file for TIAO USB Multi-Protocol Adapter.
Based on schematics from http://www.mediafire.com/?zv158nnx1gv0cy2
Cc: Volkan K <volkan-k@users.sourceforge.net>
Change-Id: I0dfd93b0b1e558e4ccd7c94c005c099947ec94df
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/1438
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
This adds support for JTAG programming by bitbanging GPIOs exposed on
the RaspberryPi's expansion header.
Tested by connecting directly to an STM32VLDiscovery board, without any
additional circuity. I observed maximum about 4MHz on the TCK pin with an
old analogue 'scope and about 100kHz when setting the speed to 100kHz.
Busyloop waiting is needed because even with a single 0ns nanosleep call
(with FIFO priority) it lowers the TCK speed to ~30kHz which is way too low
to be useful.
The speed testing with adapter_khz 2000 gave the following results:
sudo chrt -f 1 nice -n -19 ./src/openocd \
-f interface/raspberrypi-native.cfg \
-c "set WORKAREASIZE 0x2000" \
-f target/stm32f1x.cfg -c "adapter_khz 2000"
wrote 131072 bytes from file random.bin in 3.973677s (32.212 KiB/s)
dumped 131072 bytes in 1.445699s (88.538 KiB/s)
This is 3.7 times faster for writing and 14.3 times faster for reading
compared to the generic sysfsgpio driver; probably the writing speed is
limited by the target itself here and reading speed might be considerably
higher too with appropriate connection and a capable target.
BCM2835 name is choosen over BCM2708 because the published peripherals
datasheet uses the particular model name and not family name.
Change-Id: Ib78168be27f53c2a3c88c3dd8154d1190c318c78
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/758
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Updated OpenJTAG driver from www.openjtag.org to work with latest version of OpenOCD.
Change-Id: I2917f4e5835fb9ca5265e81dc38515fa97ae9503
Signed-off-by: Ryan Corbin <corbin.ryan@gmail.com>
Reviewed-on: http://openocd.zylin.com/1406
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Add target code for Andes targets.
Change-Id: Ibf0e1b61b06127ca7d9ed502d98d7e2aeebbbe82
Signed-off-by: Hsiangkai Wang <hsiangkai@gmail.com>
Reviewed-on: http://openocd.zylin.com/1259
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Andes AICE uses USB to transfer packets between OpenOCD and AICE.
It uses high-level USB commands to control targets instead of using
JTAG signals. I define an interface as aice_port_api_s. It contains
all basic operations needed by target-dependent code.
Change-Id: I117bc4f938fab2732e44c509ea68b30172d6fdb9
Signed-off-by: Hsiangkai Wang <hsiangkai@gmail.com>
Reviewed-on: http://openocd.zylin.com/1256
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This is reported as working by mitsakos on IRC.
Change-Id: I26b97779c3e8e237c5b3996aa81183031b12ec0c
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/1419
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Commit d9ba56c295 did a bunch of
renaming of cortex_a8 to cortex_a, including the names in config
files. However that introduced a regression as the name in target_type
struct remained unchanged.
This adds the last missing bit: actual renaming of the target name as
understood by OpenOCD.
Also change the (hopefully) last instance of using it in the supplied
config files, namely from imx6.cfg.
Change-Id: Ib9289fc6d946630133ec6e36c20015ccb50acf61
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/1420
Tested-by: jenkins
Reviewed-by: Chris Johns <chrisj@rtems.org>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This is needed for configs that might be used with the cheapest
STM32F100 parts that have only 4kB SRAM.
Restrictions for the other STM32 families are verified to be set
appropriately.
Change-Id: I1ad2370435015604db9f27c1a76c153480311a28
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/1378
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Due to reports of newer targets using a updated version of the ICEPick tap
rather than add another tapid we ignore the tap version.
Also see Trac 49 for details.
Change-Id: Ic78414c54af2545c817e1bb2c860970c1b587259
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1373
Tested-by: jenkins
Reviewed-by: Peter Stuge <peter@stuge.se>
Rename cortex_a8 target to use a more correct cortex_a name.
This also adds a deprecated_name var so that older scripts issue a warning
to update the target name.
cfg files have also been updated to the new target name.
Change-Id: I0eb1429c9281321efeb444b27a662a941a2ab67f
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1130
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Rename cortex_m3 target to use a more correct cortex_m name.
This also adds a deprecated_name var so that older scripts issue a warning
to update the target name.
cfg files have also been updated to the new target name.
Change-Id: Ia8429f38e88da677249c5caa560c50f8ce56ea10
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1129
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
As requested, here is the target configuration that I'm using for an
STLink-V2-attached STM32W108C8. For some reason, it only seems to work
with "reset_config trst_only".
Change-Id: Icbff4f83343e1f505d8afdfc53ff6f8b7496cac9
Signed-off-by: Ben Nahill <bnahill@gmail.com>
Reviewed-on: http://openocd.zylin.com/1347
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
By default pic32mx starts after any reset with 1 wait state for RAM access/exec.
It can be changed to 0 wait states by clearing the BMXWSDRM bit (bit 6) in BMXCON register.
With 0 wait states near doubles the execution speed. CRC check sum can be done much faster
increasing verify_image speed. Fast data transfer also works with a bit higher scan rate, up to 1500 Khz.
This option can be set at any time with
mww 0xbf882004 0x40
or cleared with
mww 0xbf882008 0x40.
Some numbers for FTDI/HS with current devel code and a elf file:
Core clock / wait states verify_image speed
------------------------------------|------------------------------
4 Mhz / 1 21 KiB/s
4 Mhz / 0 36 KiB/s
8 Mhz / 1 37 KiB/s
8 Mhz / 0 57 KiB/s
Change-Id: I4092ad0f3753f72f77108718d0ed3a3ab84e3b23
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/1141
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-by: Xiaofan <xiaofanc@gmail.com>
This config file add support to the opendous cable based on the chip ft2232H,
using the ft2232 interface driver.
Change-Id: I8171a0c475af8d61e081844ee86466a392138fb0
Signed-off-by: Rodrigo Melo <rmelo@inti.gob.ar>
Reviewed-on: http://openocd.zylin.com/1096
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This config file add support to the opendous cable based on the chip ft2232H,
using the ftdi interface driver.
Change-Id: I4491f99d7b14f7078a04583ef0c4acd8692c4349
Signed-off-by: Rodrigo Melo <rmelo@inti.gob.ar>
Reviewed-on: http://openocd.zylin.com/1097
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This change adds a simple target configuration for Freescale
single/dual/quad core i.MX6 SoCs, only one core is configured by default.
Change-Id: I853dd27f4c6765b7f731be2ddea82e85d496c6a4
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Reviewed-on: http://openocd.zylin.com/1135
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This patch change the default reset config from SYSRESETREQ to the working
VECTRESET.
Change-Id: I21a9a74b9c0c68cfa3a6e6dac9b123acc98a93cb
Signed-off-by: Mathias K <kesmtp@freenet.de>
Reviewed-on: http://openocd.zylin.com/1186
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This update adds support for the STM32Lx 384kb dual bank flash. Previously there was a problem when writing an
image that was larger than 192Kb. That lead to openocd printing out two error messages like
"Error: access denied / write protected" and "Error: invalid program address". The reason was that the stm32lx
driver tried to write half pages which overlapped into the next flash bank.
A new configuration file stm32lx_dual_bank.cfg can be used for stm32lx chips with dual bank flash (256kb or 384kb devices).
A sanity check was added for probed flash size values to fix the issue seen on some ST samples that answered incorrectly.
Change-Id: I69e25131983d88613be8606b438f98870c5f1e52
Signed-off-by: Johan Almquist <johan.almquist@assaabloy.com>
Reviewed-on: http://openocd.zylin.com/1125
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
adapter_init (core.c) won't check speed configuration
of the selected interface if it's not needed (.speed = NULL).
When it's not needed, we can now omit adapter_khz in
init scripts and we don't have to implement dummy handlers
for speed_div and khz functions.
It also removes calls to adapter_khz in interface configuration
files when not used anymore.
Change-Id: I6eb1894385503fede542a368f297cec6565eed44
Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
Reviewed-on: http://openocd.zylin.com/1131
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Limited (no page unprotect, no block writes) implementation of EFM32
flash support. Verified with EFM32 development kit and STLink V2 adapter
using SWD.
Change-Id: I3db2054d9aa628a1fe4814430425db3c9959c71c
Signed-off-by: Roman D <me@iamroman.org>
Reviewed-on: http://openocd.zylin.com/1106
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This part has 16k ram so make it all available.
Change-Id: Ifeb7bc850bfe4f68d0affb8f6a0931b4327e7257
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1006
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
The smallest pert in the family has 10k RAM, so use that as a default
for the working area.
Change-Id: I78be0d14a254c109ac15a7163552c6132f810416
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1005
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Switch to using the internal HSI when a reset init is called, this also
matches the std stm32l cfg.
Read (verify) speed is increased from 17 to 120 KiB/s.
Change-Id: Ic94ba85949ffdefa17b7be45eef14e30f941d107
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1004
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Paul Fertser
Greg Ungerer
Spencer Oliver
Franck Jullien
Pushpal Sidhu
Brad Riensche
Sergey Alirzaev
Marek Vasut
Laszlo Papp
Andreas Fritiofson
John Szakmeister
Giuseppe Barba
Ryan Corbin
Hsiangkai Wang
Ben Nahill
Peter Dietzsch
Salvador Arroyo
Rodrigo Melo
Vladimir Zapolskiy
Mathias K
Johan Almquist
Roman D