Commit Graph

6 Commits (0c8ec7c826c60391034fe5f0ea90f8538ac94b38)

Author SHA1 Message Date
Tim 'mithro' Ansell 3edb15784e tcl: Support for reading "Device DNA" from Spartan 6 devices.
Most Xilinx FPGA devices contain an embedded, unique device identifier
called the "Device DNA". The identifier is nonvolatile, permanently
programmed into the FPGA, and is unchangeable providing a great serial
/ tracking number.

Debugging was done in https://github.com/timvideos/HDMI2USB/issues/36

Change-Id: Iad03eafb40887f0321a4dc22858a7c3bf37a12b3
Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
Reviewed-on: http://openocd.zylin.com/2960
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2015-10-21 09:11:48 +01:00
Robert Jordens 733e8ba062 kc705: digilent-jtag/kintex7/jtagspi board
Xilinx Kintex7 Development board with integrated Digilent JTAG-SMT1
(a.k.a. HS1) interface and a 128 MBit SPI flash.

Change-Id: I9daba0a2fb2c17e04bcb37bd41872ebde25e0d2f
Signed-off-by: Robert Jordens <jordens@gmail.com>
Reviewed-on: http://openocd.zylin.com/2861
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-08-06 13:14:21 +01:00
Robert Jordens 804eefc259 pipistrello: ftdi-jtag/spartan6/jtagspi board
The Pipistrello is a low cost FPGA board with a Xilinx
Spartan6 LX45, a SPI flash and onboard FTDI JTAG.
This board is a good example use case for the jtagspi
flash driver talking through a proxy bitstream.

Change-Id: I04a80610ff825c36ebcb67b879507028eed141ad
Signed-off-by: Robert Jordens <jordens@gmail.com>
Reviewed-on: http://openocd.zylin.com/2846
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-08-06 13:14:13 +01:00
Robert Jordens d25355473d flash/nor/jtagspi: add JTAGSPI driver
Many FPGA board speak JTAG and have a SPI flash for their bitstream
attached to them. The SPI flash is programmed by first uploading a
proxy bitstream to the FPGA that connects the JTAG interface to the
SPI interface if the IR contains a certain USER instruction. Then the
SPI flash can be erase, written, read directly through the JTAG DR.

The JTAG and SPI signaling is compatible. Such a proxy bitstream only
needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the
chip select when the IR contains the special instruction and the JTAG
state machine is in the DR-SHIFT state.

Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2
Signed-off-by: Robert Jordens <jordens@gmail.com>
Reviewed-on: http://openocd.zylin.com/2844
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-08-06 13:14:08 +01:00
Freddie Chopin af9918deec Add config file for Lattice LC4032ZE CPLD (ispMACH 4000ZE family)
Change-Id: Iefec12b30ff737317c454b472200fd7e7edde619
Signed-off-by: Freddie Chopin <freddie.chopin@gmail.com>
Reviewed-on: http://openocd.zylin.com/748
Tested-by: jenkins
Reviewed-by: Peter Stuge <peter@stuge.se>
2012-07-17 08:29:32 +00:00
Wookey 407061eaa6 Xilinx xcr3256.cfg basic config script 2009-10-12 15:12:35 +02:00