zcy
/
tinyriscv-openocd
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
9,163 Commits
46 Branches
9 Tags
21 MiB
Commit Graph

2 Commits (tinyriscv)

Author SHA1 Message Date
Jonathan McDowell d2fb461621 Correct ZynqMP configuration to be appropriately named 
The xilinx_ultrascale.cfg target is actually the configuration for a
ZynqMP, which is a combination of an UltraScale+ FPGA core and a quad
core A53. Update the filename/comments to reflect this, and include
the tap IDs for all known FPGA cores for this part.

Change-Id: I70dfcc99861a482b83b6a795e83021d9cf1fe047
Signed-off-by: Jonathan McDowell <noodles@earth.li>
Reviewed-on: http://openocd.zylin.com/4850
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
 2019-01-23 15:26:48 +00:00
Matthias Welwarsky 7274090456 tcl/board: add configuration for the avnet ultrazed-eg starter kit 
also contains target configuration for the Xilinx UltraScale+
platform

Change-Id: I6300cbc85c1ed71df71d8aaca59500bbf18f0093
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/4467
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
 2018-03-30 09:48:35 +01:00