* Clear cmderr by writing all ones.
This should have been part of #389.
Change-Id: Ie40e95fdd904af65c53d1f5de7c8464b27038ec0
* Don't update reg cache in register_write_direct().
This function explicitly bypasses any caches.
Change-Id: Ie3c9a1163e870f80c0ed75b74495079c527663e9
* Use only one hart to run algorithm.
Fixes a bug with `-rtos hwthread` where all harts would run when running
a flash/CRC algorithm, which would probably ruin flashing, and was
unexpectedly changing registers on other harts for the CRC algorithm.
Change-Id: Ia2f600624f4c8d4cab319861fef2c14722f08b53
* Adds support for RISCV Access Memory Abstract Commands
The Access Memory Abstract Command is one of the three optional
methods for reading and writing memory on a complient RISCV
debug module. The previous two options were already implemented
in OpenOCD.
Implementation Notes:
- aamvirtual is hard-coded to false until the design for accessing
virtual addresses is finalized.
- aamsizes corresponding to 8b, 16b, 32b, and 64b are supported.
128b support is postponed until it is required, as it will mean
changes to the read/write_abstract_arg() interface to pass 128b
values.
- aampostincrement is not used and hard-coded to false.
* Changes from review.
* Additional lint fixes and a typo from last commit.
* Fixing a clang error.
* Fixes a last-minute change that broke writes with width > 8b.
* Removing memcpy after adding read_from_buf().
Fake step is a hack introduced to make things work with real RTOSs that
have a concept of a current thread. The hwthread rtos always has access
to all threads, so doesn't need it.
This fixes a bug when running my MulticoreRegTest against HiFive
Unleashed where OpenOCD would return the registers of the wrong thread
after gdb stepped a hart.
Change-Id: I64f538a133fb078c05a0c6b8121388b0b9d7f1b8
* add opcode for csrrsi and csrrci
* enable MMU while reading/writing memory using progbuf
* fix style issues
* keep old behavior for progbufsize<4, perform r/w/csr only when necessary
* do not pass progbufsize, only write mstatus if changed
* add config option to enable virtualization feature
* throw error if virt enabled but unavaliable, outsource modify_privilege
* support virtualization for read_memory_progbuf_one
gdb has developed a nasty habit of very often reading 30-some
half-words. This change speeds that up significantly.
Change-Id: Iab1b7575bec5c57051c6e630ae292dddf8fe6350
* Make resume order configurable.
This is a customer requirement. Using this option is discouraged.
Change-Id: I520ec19cc23d7837cb8576f69dadf2b922fa2628
* Fix style.
Change-Id: If8e515984c92ce8df52aa69e87abde023897409f
* Make mingw32-gcc happy.
Change-Id: I39852aedec293294b2b2638ab2cc45494fe77beb
* WIP, rewrite of flash algorithm.
Just put all the flashing logic into the algorithm, instead of using an
intermediate format. This should reduce total data written while
flashing by about 9%, and also makes the code much simpler.
Change-Id: I807e60c8ab4f9f376cceaecdbbd10a2326be1c79
* New algorithm works.
Speeds up Arty flashing another 9%.
wrote 2228224 bytes from file /media/sf_tnewsome/SiFive/arty_images/arty.E21TraceFPGAEvaluationConfig.mcs in 86.784538s (25.074 KiB/s)
verified 2192012 bytes in 6.693336s (319.816 KiB/s)
8.66user 13.03system 1:33.91elapsed 23%CPU (0avgtext+0avgdata 12272maxresident)k
Change-Id: Ie55c5250d667251be141cb32b144bbcf3713fce4
* Fix whitespace.
Change-Id: I338d518fa11a108efb530ffe75a2030619457a0b
* Don't reserve so much stack space.
Also properly check XLEN in riscv_wrapper.S.
Change-Id: Ifa0301f3ea80f648fb8a6d6b6c8bf39f386fe4a6
* In theory support RV32E.
Change-Id: Icfe2a40976ae3161f2324e5bb586915aa4c4c7ee
* In theory support RV32E.
At least very basic tests pass.
Change-Id: Ia42e28a3fa020b3e52c92109392c46d009330355
* Fix cut and paste bug.
Change-Id: Ibfea68b39d706f59a8c3aa8153bb4db9803958c6
* Add hacks to make RV32E work with gdb.
gdb currently requires all 32 GPRs to be present, even on RV32E targets.
Once gdb is fixed these hacks can be removed.
Change-Id: Idcde648de2ca1a3f5b31315aab35fac86580af2c
* Cache program buffer writes.
Speeds up flash program by 3%, flash verify by 2%.
Change-Id: I19f8f44f560a1111fa8f4e4fc04ce6de3c94999a
* Remove nop from batch reads.
program @ 22.123 KiB/s, verify @ 47.654 KiB/s (up from program @ 20.287
KiB/s, verify @ 23.148 KiB/s originally).
Change-Id: I7ee19d967b1080336b0088d20e1fc30828afd935
* Use "algorithm" to compute CRC on RISC-V targets.
Use the C compiler to generate the algorithm code. It's better at
assembly than I am. We need separate RV32 and RV64 binaries to handle
shift instructions. I used the code from gdb (libiberty really) because
it returns the correct result. I'm not sure if the table is worth it
since we do have to save/download/restore more bytes now.
riscv_run_algorithm() now properly saves and reads back all registers
used for parameters. It also doesn't check final_pc if exit_point is 0.
Using gdb means I don't know the exact address where the code will end.
Small target.[ch] change to be able to run algorithms at 64-bit
addresses.
Flashing an arty board now:
```
wrote 2228224 bytes from file /media/sf_tnewsome/SiFive/arty_images/arty.E21TraceFPGAEvaluationConfig.mcs in 105.589180s (20.608 KiB/s)
verified 2192012 bytes in 7.037476s (304.177 KiB/s)
9.87user 16.16system 1:53.16elapsed 23%CPU (0avgtext+0avgdata 24768maxresident)k
```
Change-Id: I6696bd4cda7c89ac5ccd21b2ff3aa1663d7d7190
* Clean up formatting.
Change-Id: I7f2d792a2b9432a04209272abb00d8136ee01025
* Inverted Frame to Pseudo Tap for Simpler Hardware to Decode
Given the variable supported message length , a prefix decoding approach is significantly simpler for a pseudo tap architecture with a shift reg of len = max len of packet. This prefix coding packet also makes the message len field redundant , as that is implict in ir_len and the ir selected.
* style patch
* non-conflict with original
* style patch
* style patch
* requested changes
* style-patch
* Fix small SBA bug.
We were not compliant with the spec, but I'm not sure if this was
causing problems for anybody.
Change-Id: Ia31ee400fd75ad907349c4dd995b1e03bd2116c7
* Don't write sbcs while sbbusy is set.
Probably not hurting anything, but the spec says we shouldn't.
Also propagate more errors, and fully decode sbcs in debug output.
Change-Id: I1a36646772fe794c8780702565103a309bbcc5e9
This messes up all kinds of tests against HiFive Unleashed, because some
harts may be single stepped from previous tests. The symptom is that gdb
will suddenly be accessing a different hart than you think it is.
I replaced it with a comment so I can remember what happened when time
comes to upstream this change. It may not be acceptable depending on
what the reason for the call is in the first place.
Change-Id: I1fb44d5a7792835f66342f590a5f7bbf8c21b64e
Currently the RISC-V compliance test suite doesn't output the test is
currently runs before it succeeds. It also uses the same message for
many tests. This makes it very hard to find out which test fails.
This commit makes things slightly easier by printing the test that's
being executed before it actually runs, and by adding the source code
line where the test is located, making it easier to look up the test in
the source code.
New output looks like this:
Info : Executing test 149 (riscv-013.c:3800): Regular calls must return ERROR_OK
Info : PASSED
The test assumes that the target has been examined. If that fails (for
whatever reason) the test will segfault:
Program received signal SIGSEGV, Segmentation fault.
register_cache_invalidate (cache=0x0) at ../src/target/register.c:109
109 struct reg *reg = cache->reg_list;
(gdb) bt
0 register_cache_invalidate (cache=0x0) at ../src/target/register.c:109
1 0x0000000000520735 in riscv_invalidate_register_cache (target=target@entry=0x779b50) at ../src/target/riscv/riscv.c:2160
2 0x000000000052224f in riscv_halt_all_harts (target=target@entry=0x779b50) at ../src/target/riscv/riscv.c:2022
3 0x0000000000574e82 in riscv013_test_compliance (target=0x779b50) at ../src/target/riscv/riscv-013.c:3600
* Remove unnecessary 0.11 code.
Don't need need_strict_step anymore now that we have
riscv_hit_watchpoint().
Don't need 32-bit warning in riscv011_resume() now that address is a
target_address_t.
Change-Id: I375c023a7ec9f62d80b037ddb64d14526ba0a3dc
* WIP little refactor working towards hasel support.
Change-Id: Ie0b8dfd9e5ae2e36613fa00e14c3cd32749141bf
* More refactoring.
Change-Id: I083387c2ecff78ddfea3ed5078444732d77b909b
* More refactoring.
Change-Id: Icea1308499492da51354f89e1529353e8385f3a1
* Starting to work towards actual hasel changes.
Change-Id: If0df05ffa66cc58400b4855f9630a8b1bae3030e
* Implement simultaneous resume using hasel.
Change-Id: I97971d7564fdb159d2052393c8b82a2ffaa8833f
* Add support back for targets that don't have hasel.
Change-Id: I6d5439f0615d5d5333127d280e4f2642649a119a
* Make hasel work with >32 harts.
Change-Id: I3c55009d48bfc5dd62e3341df4e4bd21df2fe44f
Depending on how the MMU is configured it is possible to have a 1:1
mapping between virtual and physical addresses, thus making this warning
bogus. We already check that the MMU is enabled in the caller:
cortex_a_virt2phys().
Change-Id: I09f4c53ef933c8d1e268da5215a769449be014bc
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Reviewed-on: http://openocd.zylin.com/5007
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Kamal Dasu <kdasu.kdev@gmail.com>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Remove the target halted check from cortex_m_remove_breakpoint()
as there is no such check in cortex_m_set_breakpoint() and bp can be
safely removed from the running target.
While on it return the error code from cortex_m_unset_breakpoint()
to higher level.
Change-Id: I2b358c3661feed84297913e9f589bdf1e4de7e64
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4887
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-by: Jānis Skujenieks <janis.skujenieks@gmail.com>
Reviewed-by: Christopher Head <chead@zaber.com>
fp_code_available looses sync with the real number of free comparators
as soon as cortex_m_set_breakpoint() returns an error. Remove the counter
and always go through the fp_comparator_list to find a free one.
Change-Id: I9f6e06c36d8a57ad11df5155e8a1a3aff6d833a5
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4870
Tested-by: jenkins
Reviewed-by: Jānis Skujenieks <janis.skujenieks@gmail.com>
Reviewed-by: Christopher Head <chead@zaber.com>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Cortex-M uses only 2 byte breakpoint instruction.
cortex_m_unset_breakpoint() does not need to check breakpoint->length,
use the length as the size argument in target_write_memory()
Change-Id: I20bb869f6abce2fc61f0469e34a638bc4dc6f7ce
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4889
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-by: Jānis Skujenieks <janis.skujenieks@gmail.com>
Reviewed-by: Christopher Head <chead@zaber.com>
Instances of struct flash_driver are never written to at runtime. For a
small amount of memory saving and also robustness (fewer things for
stray pointer writes to hit), mark them const.
Change-Id: Iadbbbc2fac0976d892699200000c5f02856729f3
Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/4803
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
The code for this command is currently replicated in cortex_a and
in mips_m4k and is going to be added again for cortex_m.
Plus, it is going to be obsoleted by the HW thread pseudo RTOS.
Consolidate in smp.c a single instance of the command. This will
simplify both obsoleting it and adding it to cortex_m, whatever
change comes first.
Change-Id: I03cd857e21fa3f7202fdcee36bcbd5aae30a609d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/4991
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Seams over-engineered having two separate commands to turn SMP
on/off. Plus it is missing the possibility to dump the current
status of SMP and would be weird adding an additional command
for it. Moreover, such commands are replicated in few targets so
it would make sense centralizing them.
- Deprecate the commands "smp_on" and "smp_off".
- Add a new command "smp" that accepts optional parameters
"[on|off]" and prints the SMP status when run without
parameters. This replaces the two commands above.
- Put the deprecated and the new command handlers in smp.c
- Update the documentation, except for mips_m4k, since it is not
available yet.
- Promote the macro foreach_smp_target to global context and use
it where possible.
Change-Id: Ia72841c1a3bd6edd4db4cc809046322f498617e6
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/4615
Tested-by: jenkins
Reviewed-by: Graham Sanderson <graham.sanderson@gmail.com>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
The imx8m also has a Cortex m4 so add a target for it.
Change-Id: I2abf62b6232c547fe9b12507f459835b11c63a6d
Signed-off-by: Angus Ainslie <angus@akkea.ca>
Reviewed-on: http://openocd.zylin.com/4501
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Use target_addr_t exclusively for comparison of sector boudaries and
address range.
Use the last addres for both address range end and sector end.
It avoids problems with a flash bank mapped at the very end of
target address space.
Change-Id: Idf97c837453d97cbc4cf8a1c76ad799f4142f19e
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4985
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
This represents months of continuing RISC-V work, with too many changes
to list individually. Some improvements:
* Fixed memory leaks.
* Better handling of dbus timeouts.
* Add `riscv expose_custom` command.
* Somewhat deal with cache coherency.
* Deal with more timeouts during block memory accesses.
* Basic debug compliance test.
* Tell gdb which watchpoint hit.
* SMP support for use with -rtos hwthread
* Add `riscv set_ir`
Change-Id: Ica507ee2a57eaf51b578ab1d9b7de71512fdf47f
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: http://openocd.zylin.com/4922
Tested-by: jenkins
Reviewed-by: Philipp Guehring <pg@futureware.at>
Reviewed-by: Liviu Ionescu <ilg@livius.net>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Some boards require a slower clock speed because of passive components on the
JTAG/SWD lines. The previous implementation would first try to discover the
chips on the default speed, and only after discovery switch to the requested
adapter_khz speed.
This patch moves the speed change to just before entering the SWD/JTAG mode,
which should alleviate this problem.
Tested on an STLink V2 clone.
Change-Id: I9734452dcc8bb28d6629e64d9a7e32ef92868cf9
Signed-off-by: Frans-Willem Hardijzer <fw@hardijzer.nl>
Reviewed-on: http://openocd.zylin.com/4818
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Fix indent of the macros in header file, no functional change.
Change-Id: I4d1dba5725155200148d1543c45bad919f6cd37e
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-on: http://openocd.zylin.com/4995
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
These macros are missing parenthesis around the argument, which can
lead to side effects, add them. Replace the argument name to avoid
conflict with uint32_t data type, since the macro can be applied to
other data types as well.
Change-Id: I32d2ffec6c062795d7c8bb23d1dfa3378bfc3a58
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-on: http://openocd.zylin.com/4994
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Bit 4 in OPTSR is IWDG1_SW (the code originally called it IWDG1_HW, but
the reference manual refers to it as IWDG1_SW). This is broken out into
a separate variable, independent_watchdog_selection, in stm32x_options.
However, this is not necessary: bit 4 is included in the user_options
field, which includes all of bits 2 through 7, and
independent_watchdog_selection is not referenced anywhere else. Delete
the field and just rely on user_options to transport that bit, along
with all the other bits it contains, between stm32x_read_options and
stm32x_write_options.
Change-Id: I4da63df9272cf091267b956c412b95671ea1d3c9
Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/4744
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Write to register DP_SELECT can fail, but both functions
swd_queue_dp_bankselect() and swd_queue_ap_bankselect() return
void and do not propagate the error.
Change the return type of the two functions to int and check the
returned value.
Invalidate the cached value of DP_SELECT if the write fails.
Change-Id: Iba6ef8b0c2332e7f7efb66337d558fb7a4a0d39c
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/4980
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
When the register DP_SELECT is written directly, e.g. with command
<dap> dpreg 8 <value>
the cached value in OpenOCD is not completely updated with the new
value, thus creating issues in the following AP and DP read/write
that rely on the cached value.
Update the cached value while writing to DP_SELECT.
Change-Id: I8221b10cd6fc1fbe73e6b834b68820b43480e1a2
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/4979
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
cgsfv
Tim Newsome
dave-estes-syzexion
Nils Wistoff
jhjung81
Paul George
Philipp Wagner
Greg Savin
Florian Fainelli
Tomas Vanek
Christopher Head
Antonio Borneo
Angus Ainslie
Frans-Willem Hardijzer
Marek Vasut
Marc Schink