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pipistrello: decrease jtag speed to 10 MHz 

30 MHz is not working reliably here

Change-Id: I38f5f8c7153fc64e313ee911b1629fb5f1114c39
Signed-off-by: Robert Jordens <jordens@gmail.com>
Reviewed-on: http://openocd.zylin.com/4242
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
riscv-compliance-dev
Robert Jordens 2017-10-05 15:44:58 +02:00 committed by Tomas Vanek
parent 06e13d6ff5
commit fd6986168a
1 changed files with 1 additions and 1 deletions
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2
tcl/interface/ftdi/pipistrello.cfg
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@ -10,4 +10,4 @@ ftdi_layout_init 0x0008 0x000b
reset_config none
# this generally works fast: the fpga can handle 30MHz, the spi flash can handle
# 54MHz with simple read, no dummy cycles, and wait-for-write-completion
adapter_khz 30000
adapter_khz 10000