Propagate register read errors.
Change-Id: Idda111377873a2236b5b91e4ffdabd2be384b47arbb_cleanup
Tim Newsome
parent
0e3869cbf6
commit
fd506fa839
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@ -281,7 +281,12 @@ static int riscv_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, char
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*hex_reg_list[0] = '\0';
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for (size_t i = 0; i < n_regs; ++i) {
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if (riscv_has_register(rtos->target, thread_id, i)) {
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uint64_t reg_value = riscv_get_register_on_hart(rtos->target, thread_id - 1, i);
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uint64_t reg_value;
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int result = riscv_get_register_on_hart(rtos->target, ®_value,
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thread_id - 1, i);
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if (result != ERROR_OK)
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return JIM_ERR;
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for (size_t byte = 0; byte < xlen / 8; ++byte) {
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uint8_t reg_byte = reg_value >> (byte * 8);
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char hex[3] = {'x', 'x', 'x'};
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@ -47,7 +47,9 @@ int riscv_program_exec(struct riscv_program *p, struct target *t)
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for (size_t i = GDB_REGNO_ZERO + 1; i <= GDB_REGNO_XPR31; ++i) {
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if (p->writes_xreg[i]) {
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LOG_DEBUG("Saving register %d as used by program", (int)i);
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saved_registers[i] = riscv_get_register(t, i);
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int result = riscv_get_register(t, &saved_registers[i], i);
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if (result != ERROR_OK)
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return result;
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}
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}
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@ -217,7 +217,8 @@ typedef struct {
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static int poll_target(struct target *target, bool announce);
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static int riscv011_poll(struct target *target);
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static riscv_reg_t get_register(struct target *target, int hartid, int regid);
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static int get_register(struct target *target, riscv_reg_t *value, int hartid,
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int regid);
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/*** Utility functions. ***/
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@ -1180,8 +1181,8 @@ static int update_mstatus_actual(struct target *target)
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/* Force reading the register. In that process mstatus_actual will be
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* updated. */
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get_register(target, 0, GDB_REGNO_MSTATUS);
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return ERROR_OK;
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riscv_reg_t mstatus;
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return get_register(target, &mstatus, 0, GDB_REGNO_MSTATUS);
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}
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/*** OpenOCD target functions. ***/
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@ -1285,22 +1286,22 @@ static int register_write(struct target *target, unsigned int number,
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return ERROR_OK;
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}
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static riscv_reg_t get_register(struct target *target, int hartid, int regid)
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static int get_register(struct target *target, riscv_reg_t *value, int hartid,
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int regid)
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{
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assert(hartid == 0);
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riscv011_info_t *info = get_info(target);
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maybe_write_tselect(target);
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riscv_reg_t value = ~0;
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if (regid <= GDB_REGNO_XPR31) {
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value = reg_cache_get(target, regid);
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*value = reg_cache_get(target, regid);
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} else if (regid == GDB_REGNO_PC) {
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value = info->dpc;
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*value = info->dpc;
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} else if (regid >= GDB_REGNO_FPR0 && regid <= GDB_REGNO_FPR31) {
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int result = update_mstatus_actual(target);
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if (result != ERROR_OK)
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return ~0;
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return result;
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unsigned i = 0;
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if ((info->mstatus_actual & MSTATUS_FS) == 0) {
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info->mstatus_actual = set_field(info->mstatus_actual, MSTATUS_FS, 1);
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@ -1316,17 +1317,19 @@ static riscv_reg_t get_register(struct target *target, int hartid, int regid)
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cache_set_jump(target, i++);
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if (cache_write(target, 4, true) != ERROR_OK)
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return ~0;
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return ERROR_FAIL;
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} else if (regid == GDB_REGNO_PRIV) {
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value = get_field(info->dcsr, DCSR_PRV);
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} else if (register_read(target, &value, regid) != ERROR_OK) {
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value = ~0;
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*value = get_field(info->dcsr, DCSR_PRV);
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} else {
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int result = register_read(target, value, regid);
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if (result != ERROR_OK)
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return result;
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}
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if (regid == GDB_REGNO_MSTATUS)
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target->reg_cache->reg_list[regid].valid = true;
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return value;
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return ERROR_OK;
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}
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static int set_register(struct target *target, int hartid, int regid,
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@ -30,20 +30,21 @@
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#define DMI_DATA1 (DMI_DATA0 + 1)
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#define DMI_PROGBUF1 (DMI_PROGBUF0 + 1)
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static void riscv013_on_step_or_resume(struct target *target, bool step);
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static int riscv013_on_step_or_resume(struct target *target, bool step);
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static int riscv013_step_or_resume_current_hart(struct target *target, bool step);
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static void riscv013_clear_abstract_error(struct target *target);
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/* Implementations of the functions in riscv_info_t. */
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static riscv_reg_t riscv013_get_register(struct target *target, int hartid, int regid);
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static int riscv013_get_register(struct target *target,
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riscv_reg_t *value, int hid, int rid);
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static int riscv013_set_register(struct target *target, int hartid, int regid, uint64_t value);
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static void riscv013_select_current_hart(struct target *target);
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static int riscv013_halt_current_hart(struct target *target);
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static int riscv013_resume_current_hart(struct target *target);
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static int riscv013_step_current_hart(struct target *target);
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static void riscv013_on_halt(struct target *target);
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static void riscv013_on_step(struct target *target);
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static void riscv013_on_resume(struct target *target);
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static int riscv013_on_halt(struct target *target);
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static int riscv013_on_step(struct target *target);
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static int riscv013_on_resume(struct target *target);
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static bool riscv013_is_halted(struct target *target);
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static enum riscv_halt_reason riscv013_halt_reason(struct target *target);
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static int riscv013_write_debug_buffer(struct target *target, unsigned index,
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@ -1855,36 +1856,37 @@ struct target_type riscv013_target = {
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};
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/*** 0.13-specific implementations of various RISC-V helper functions. ***/
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static riscv_reg_t riscv013_get_register(struct target *target, int hid, int rid)
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static int riscv013_get_register(struct target *target,
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riscv_reg_t *value, int hid, int rid)
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{
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LOG_DEBUG("reading register %s on hart %d", gdb_regno_name(rid), hid);
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riscv_set_current_hartid(target, hid);
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uint64_t out;
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riscv013_info_t *info = get_info(target);
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int result = ERROR_OK;
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if (rid <= GDB_REGNO_XPR31) {
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register_read_direct(target, &out, rid);
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result = register_read_direct(target, value, rid);
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} else if (rid == GDB_REGNO_PC) {
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register_read_direct(target, &out, GDB_REGNO_DPC);
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LOG_DEBUG("read PC from DPC: 0x%016" PRIx64, out);
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result = register_read_direct(target, value, GDB_REGNO_DPC);
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LOG_DEBUG("read PC from DPC: 0x%016" PRIx64, *value);
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} else if (rid == GDB_REGNO_PRIV) {
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uint64_t dcsr;
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register_read_direct(target, &dcsr, GDB_REGNO_DCSR);
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buf_set_u64((unsigned char *)&out, 0, 8, get_field(dcsr, CSR_DCSR_PRV));
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result = register_read_direct(target, &dcsr, GDB_REGNO_DCSR);
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buf_set_u64((unsigned char *)value, 0, 8, get_field(dcsr, CSR_DCSR_PRV));
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} else {
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int result = register_read_direct(target, &out, rid);
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result = register_read_direct(target, value, rid);
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if (result != ERROR_OK) {
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LOG_ERROR("Unable to read register %d", rid);
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out = -1;
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*value = -1;
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}
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if (rid == GDB_REGNO_MSTATUS)
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info->mstatus_actual = out;
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info->mstatus_actual = *value;
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}
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return out;
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return result;
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}
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static int riscv013_set_register(struct target *target, int hid, int rid, uint64_t value)
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@ -1969,18 +1971,19 @@ static int riscv013_step_current_hart(struct target *target)
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return riscv013_step_or_resume_current_hart(target, true);
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}
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static void riscv013_on_resume(struct target *target)
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static int riscv013_on_resume(struct target *target)
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{
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return riscv013_on_step_or_resume(target, false);
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}
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static void riscv013_on_step(struct target *target)
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static int riscv013_on_step(struct target *target)
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{
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return riscv013_on_step_or_resume(target, true);
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}
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static void riscv013_on_halt(struct target *target)
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static int riscv013_on_halt(struct target *target)
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{
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return ERROR_OK;
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}
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static bool riscv013_is_halted(struct target *target)
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@ -1995,7 +1998,11 @@ static bool riscv013_is_halted(struct target *target)
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static enum riscv_halt_reason riscv013_halt_reason(struct target *target)
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{
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uint64_t dcsr = riscv_get_register(target, GDB_REGNO_DCSR);
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riscv_reg_t dcsr;
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int result = register_read_direct(target, &dcsr, GDB_REGNO_DCSR);
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if (result != ERROR_OK)
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return RISCV_HALT_UNKNOWN;
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switch (get_field(dcsr, CSR_DCSR_CAUSE)) {
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case CSR_DCSR_CAUSE_SWBP:
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case CSR_DCSR_CAUSE_TRIGGER:
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@ -2064,7 +2071,7 @@ int riscv013_dmi_write_u64_bits(struct target *target)
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}
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/* Helper Functions. */
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static void riscv013_on_step_or_resume(struct target *target, bool step)
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static int riscv013_on_step_or_resume(struct target *target, bool step)
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{
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struct riscv_program program;
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riscv_program_init(&program, target);
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@ -2073,12 +2080,15 @@ static void riscv013_on_step_or_resume(struct target *target, bool step)
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LOG_ERROR("Unable to execute fence.i");
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/* We want to twiddle some bits in the debug CSR so debugging works. */
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uint64_t dcsr = riscv_get_register(target, GDB_REGNO_DCSR);
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riscv_reg_t dcsr;
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int result = register_read_direct(target, &dcsr, GDB_REGNO_DCSR);
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if (result != ERROR_OK)
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return result;
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dcsr = set_field(dcsr, CSR_DCSR_STEP, step);
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dcsr = set_field(dcsr, CSR_DCSR_EBREAKM, 1);
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dcsr = set_field(dcsr, CSR_DCSR_EBREAKS, 1);
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dcsr = set_field(dcsr, CSR_DCSR_EBREAKU, 1);
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riscv_set_register(target, GDB_REGNO_DCSR, dcsr);
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return riscv_set_register(target, GDB_REGNO_DCSR, dcsr);
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}
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static int riscv013_step_or_resume_current_hart(struct target *target, bool step)
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@ -320,8 +320,10 @@ static int maybe_add_trigger_t1(struct target *target, unsigned hartid,
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riscv_set_register_on_hart(target, hartid, GDB_REGNO_TDATA1, tdata1);
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riscv_reg_t tdata1_rb = riscv_get_register_on_hart(target, hartid,
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GDB_REGNO_TDATA1);
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riscv_reg_t tdata1_rb;
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if (riscv_get_register_on_hart(target, &tdata1_rb, hartid,
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GDB_REGNO_TDATA1) != ERROR_OK)
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return ERROR_FAIL;
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LOG_DEBUG("tdata1=0x%" PRIx64, tdata1_rb);
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if (tdata1 != tdata1_rb) {
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@ -370,7 +372,10 @@ static int maybe_add_trigger_t2(struct target *target, unsigned hartid,
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riscv_set_register_on_hart(target, hartid, GDB_REGNO_TDATA1, tdata1);
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uint64_t tdata1_rb = riscv_get_register_on_hart(target, hartid, GDB_REGNO_TDATA1);
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uint64_t tdata1_rb;
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int result = riscv_get_register_on_hart(target, &tdata1_rb, hartid, GDB_REGNO_TDATA1);
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if (result != ERROR_OK)
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return result;
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LOG_DEBUG("tdata1=0x%" PRIx64, tdata1_rb);
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if (tdata1 != tdata1_rb) {
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@ -405,8 +410,10 @@ static int add_trigger(struct target *target, struct trigger *trigger)
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continue;
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if (first_hart < 0)
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first_hart = hartid;
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tselect[hartid] = riscv_get_register_on_hart(target, hartid,
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GDB_REGNO_TSELECT);
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int result = riscv_get_register_on_hart(target, &tselect[hartid],
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hartid, GDB_REGNO_TSELECT);
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if (result != ERROR_OK)
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return result;
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}
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assert(first_hart >= 0);
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@ -417,10 +424,14 @@ static int add_trigger(struct target *target, struct trigger *trigger)
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riscv_set_register_on_hart(target, first_hart, GDB_REGNO_TSELECT, i);
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uint64_t tdata1 = riscv_get_register_on_hart(target, first_hart, GDB_REGNO_TDATA1);
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uint64_t tdata1;
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int result = riscv_get_register_on_hart(target, &tdata1, first_hart,
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GDB_REGNO_TDATA1);
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if (result != ERROR_OK)
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return result;
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int type = get_field(tdata1, MCONTROL_TYPE(riscv_xlen(target)));
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int result = ERROR_OK;
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result = ERROR_OK;
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for (int hartid = first_hart; hartid < riscv_count_harts(target); ++hartid) {
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if (!riscv_hart_enabled(target, hartid))
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continue;
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@ -533,7 +544,10 @@ static int remove_trigger(struct target *target, struct trigger *trigger)
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for (int hartid = first_hart; hartid < riscv_count_harts(target); ++hartid) {
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if (!riscv_hart_enabled(target, hartid))
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continue;
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riscv_reg_t tselect = riscv_get_register_on_hart(target, hartid, GDB_REGNO_TSELECT);
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riscv_reg_t tselect;
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int result = riscv_get_register_on_hart(target, &tselect, hartid, GDB_REGNO_TSELECT);
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if (result != ERROR_OK)
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return result;
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riscv_set_register_on_hart(target, hartid, GDB_REGNO_TSELECT, i);
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riscv_set_register_on_hart(target, hartid, GDB_REGNO_TDATA1, 0);
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riscv_set_register_on_hart(target, hartid, GDB_REGNO_TSELECT, tselect);
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@ -1553,17 +1567,20 @@ int riscv_set_register_on_hart(struct target *target, int hartid,
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return r->set_register(target, hartid, regid, value);
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}
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riscv_reg_t riscv_get_register(struct target *target, enum gdb_regno r)
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int riscv_get_register(struct target *target, riscv_reg_t *value,
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enum gdb_regno r)
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{
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return riscv_get_register_on_hart(target, riscv_current_hartid(target), r);
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return riscv_get_register_on_hart(target, value,
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riscv_current_hartid(target), r);
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}
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uint64_t riscv_get_register_on_hart(struct target *target, int hartid, enum gdb_regno regid)
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int riscv_get_register_on_hart(struct target *target, riscv_reg_t *value,
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int hartid, enum gdb_regno regid)
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{
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RISCV_INFO(r);
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uint64_t value = r->get_register(target, hartid, regid);
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LOG_DEBUG("[%d] %s: %" PRIx64, hartid, gdb_regno_name(regid), value);
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return value;
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int result = r->get_register(target, value, hartid, regid);
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LOG_DEBUG("[%d] %s: %" PRIx64, hartid, gdb_regno_name(regid), *value);
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return result;
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}
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bool riscv_is_halted(struct target *target)
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@ -1669,22 +1686,32 @@ int riscv_enumerate_triggers(struct target *target)
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if (!riscv_hart_enabled(target, hartid))
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continue;
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riscv_reg_t tselect = riscv_get_register_on_hart(target, hartid,
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riscv_reg_t tselect;
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int result = riscv_get_register_on_hart(target, &tselect, hartid,
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GDB_REGNO_TSELECT);
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if (result != ERROR_OK)
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return result;
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for (unsigned t = 0; t < RISCV_MAX_TRIGGERS; ++t) {
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r->trigger_count[hartid] = t;
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riscv_set_register_on_hart(target, hartid, GDB_REGNO_TSELECT, t);
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uint64_t tselect_rb = riscv_get_register_on_hart(target, hartid,
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uint64_t tselect_rb;
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result = riscv_get_register_on_hart(target, &tselect_rb, hartid,
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GDB_REGNO_TSELECT);
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if (result != ERROR_OK)
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return result;
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/* Mask off the top bit, which is used as tdrmode in old
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* implementations. */
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tselect_rb &= ~(1ULL << (riscv_xlen(target)-1));
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if (tselect_rb != t)
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break;
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uint64_t tdata1 = riscv_get_register_on_hart(target, hartid,
|
||||
uint64_t tdata1;
|
||||
result = riscv_get_register_on_hart(target, &tdata1, hartid,
|
||||
GDB_REGNO_TDATA1);
|
||||
if (result != ERROR_OK)
|
||||
return result;
|
||||
|
||||
int type = get_field(tdata1, MCONTROL_TYPE(riscv_xlen(target)));
|
||||
switch (type) {
|
||||
case 1:
|
||||
|
|
@ -1760,7 +1787,10 @@ const char *gdb_regno_name(enum gdb_regno regno)
|
|||
static int register_get(struct reg *reg)
|
||||
{
|
||||
struct target *target = (struct target *) reg->arch_info;
|
||||
uint64_t value = riscv_get_register(target, reg->number);
|
||||
uint64_t value;
|
||||
int result = riscv_get_register(target, &value, reg->number);
|
||||
if (result != ERROR_OK)
|
||||
return result;
|
||||
buf_set_u64(reg->value, 0, reg->size, value);
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -88,7 +88,8 @@ typedef struct {
|
|||
|
||||
/* Helper functions that target the various RISC-V debug spec
|
||||
* implementations. */
|
||||
riscv_reg_t (*get_register)(struct target *, int hartid, int regid);
|
||||
int (*get_register)(struct target *target,
|
||||
riscv_reg_t *value, int hid, int rid);
|
||||
int (*set_register)(struct target *, int hartid, int regid,
|
||||
uint64_t value);
|
||||
void (*select_current_hart)(struct target *);
|
||||
|
|
@ -96,9 +97,9 @@ typedef struct {
|
|||
int (*halt_current_hart)(struct target *);
|
||||
int (*resume_current_hart)(struct target *target);
|
||||
int (*step_current_hart)(struct target *target);
|
||||
void (*on_halt)(struct target *target);
|
||||
void (*on_resume)(struct target *target);
|
||||
void (*on_step)(struct target *target);
|
||||
int (*on_halt)(struct target *target);
|
||||
int (*on_resume)(struct target *target);
|
||||
int (*on_step)(struct target *target);
|
||||
enum riscv_halt_reason (*halt_reason)(struct target *target);
|
||||
int (*write_debug_buffer)(struct target *target, unsigned index,
|
||||
riscv_insn_t d);
|
||||
|
|
@ -205,8 +206,10 @@ bool riscv_has_register(struct target *target, int hartid, int regid);
|
|||
* are zero extended to 64 bits. */
|
||||
int riscv_set_register(struct target *target, enum gdb_regno i, riscv_reg_t v);
|
||||
int riscv_set_register_on_hart(struct target *target, int hid, enum gdb_regno rid, uint64_t v);
|
||||
riscv_reg_t riscv_get_register(struct target *target, enum gdb_regno i);
|
||||
riscv_reg_t riscv_get_register_on_hart(struct target *target, int hid, enum gdb_regno rid);
|
||||
int riscv_get_register(struct target *target, riscv_reg_t *value,
|
||||
enum gdb_regno r);
|
||||
int riscv_get_register_on_hart(struct target *target, riscv_reg_t *value,
|
||||
int hartid, enum gdb_regno regid);
|
||||
|
||||
/* Checks the state of the current hart -- "is_halted" checks the actual
|
||||
* on-device register. */
|
||||
|
|
|
|||
Loading…
Reference in New Issue