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Merge pull request #91 from riscv/info 

Be more clear in multi-core systems without -rtos
macbuild
Tim Newsome 2017-09-19 12:53:02 -07:00 committed by GitHub
parent deaf2d7663 157a67a98a
commit fd2d2d0aa3
1 changed files with 7 additions and 3 deletions
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10
src/target/riscv/riscv-013.c
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@ -1175,9 +1175,13 @@ static int examine(struct target *target)
LOG_INFO("Examined RISC-V core; found %d harts",
riscv_count_harts(target));
for (int i = 0; i < riscv_count_harts(target); ++i) {
LOG_INFO(" hart %d: XLEN=%d, program buffer at 0x%" PRIx64
", %d triggers", i, r->xlen[i], r->debug_buffer_addr[i],
r->trigger_count[i]);
if (riscv_hart_enabled(target, i)) {
LOG_INFO(" hart %d: XLEN=%d, program buffer at 0x%" PRIx64
", %d triggers", i, r->xlen[i], r->debug_buffer_addr[i],
r->trigger_count[i]);
} else {
LOG_INFO(" hart %d: currently disabled", i);
}
}
return ERROR_OK;
}