ARM: simplify ARMv7-A register handling
ARMv7-A doesn't need to duplicate all the standard ARM code for register handling. - Switch Cortex-A8 to use the standard register code - Remove duplicated infrastructure from ARMv7-A - Have ARMv7-A arch_state() show CPSR, like other ARMs Add comments to show where the Cortex-A8 isn't actually doing the right thing for register reads/writes, unless core happens to be in the right mode to start with. (Looks like maybe there may be generic confusion between saved/current PSR values in all the ARM code ...) Make related ARMv7-A and Cortex-A8 symbols properly static. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>__archive__
David Brownell
parent
8a6d4ced4c
commit
f5093e1605
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@ -34,108 +34,12 @@
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#include <unistd.h>
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char* armv7a_core_reg_list[] =
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{
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"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
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"r8", "r9", "r10", "r11", "r12", "r13_usr", "lr_usr", "pc",
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"r8_fiq", "r9_fiq", "r10_fiq", "r11_fiq", "r12_fiq", "r13_fiq", "lr_fiq",
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"r13_irq", "lr_irq",
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"r13_svc", "lr_svc",
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"r13_abt", "lr_abt",
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"r13_und", "lr_und",
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"cpsr", "spsr_fiq", "spsr_irq", "spsr_svc", "spsr_abt", "spsr_und",
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"r13_mon", "lr_mon", "spsr_mon"
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};
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char* armv7a_state_strings[] =
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static const char *armv7a_state_strings[] =
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{
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"ARM", "Thumb", "Jazelle", "ThumbEE"
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};
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struct armv7a_core_reg armv7a_core_reg_list_arch_info[] =
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{
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{0, ARMV4_5_MODE_ANY, NULL, NULL},
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{1, ARMV4_5_MODE_ANY, NULL, NULL},
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{2, ARMV4_5_MODE_ANY, NULL, NULL},
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{3, ARMV4_5_MODE_ANY, NULL, NULL},
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{4, ARMV4_5_MODE_ANY, NULL, NULL},
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{5, ARMV4_5_MODE_ANY, NULL, NULL},
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{6, ARMV4_5_MODE_ANY, NULL, NULL},
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{7, ARMV4_5_MODE_ANY, NULL, NULL},
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{8, ARMV4_5_MODE_ANY, NULL, NULL},
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{9, ARMV4_5_MODE_ANY, NULL, NULL},
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{10, ARMV4_5_MODE_ANY, NULL, NULL},
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{11, ARMV4_5_MODE_ANY, NULL, NULL},
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{12, ARMV4_5_MODE_ANY, NULL, NULL},
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{13, ARMV4_5_MODE_USR, NULL, NULL},
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{14, ARMV4_5_MODE_USR, NULL, NULL},
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{15, ARMV4_5_MODE_ANY, NULL, NULL},
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{8, ARMV4_5_MODE_FIQ, NULL, NULL},
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{9, ARMV4_5_MODE_FIQ, NULL, NULL},
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{10, ARMV4_5_MODE_FIQ, NULL, NULL},
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{11, ARMV4_5_MODE_FIQ, NULL, NULL},
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{12, ARMV4_5_MODE_FIQ, NULL, NULL},
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{13, ARMV4_5_MODE_FIQ, NULL, NULL},
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{14, ARMV4_5_MODE_FIQ, NULL, NULL},
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{13, ARMV4_5_MODE_IRQ, NULL, NULL},
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{14, ARMV4_5_MODE_IRQ, NULL, NULL},
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{13, ARMV4_5_MODE_SVC, NULL, NULL},
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{14, ARMV4_5_MODE_SVC, NULL, NULL},
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{13, ARMV4_5_MODE_ABT, NULL, NULL},
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{14, ARMV4_5_MODE_ABT, NULL, NULL},
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{13, ARMV4_5_MODE_UND, NULL, NULL},
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{14, ARMV4_5_MODE_UND, NULL, NULL},
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{16, ARMV4_5_MODE_ANY, NULL, NULL},
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{16, ARMV4_5_MODE_FIQ, NULL, NULL},
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{16, ARMV4_5_MODE_IRQ, NULL, NULL},
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{16, ARMV4_5_MODE_SVC, NULL, NULL},
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{16, ARMV4_5_MODE_ABT, NULL, NULL},
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{16, ARMV4_5_MODE_UND, NULL, NULL},
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{13, ARMV7A_MODE_MON, NULL, NULL},
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{14, ARMV7A_MODE_MON, NULL, NULL},
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{16, ARMV7A_MODE_MON, NULL, NULL}
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};
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/* map core mode (USR, FIQ, ...) and register number to indizes into the register cache */
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int armv7a_core_reg_map[8][17] =
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{
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{ /* USR */
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0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
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},
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{ /* FIQ */
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0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 15, 32
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},
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{ /* IRQ */
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0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 23, 24, 15, 33
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},
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{ /* SVC */
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0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 25, 26, 15, 34
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},
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{ /* ABT */
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0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 28, 15, 35
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},
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{ /* UND */
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0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 29, 30, 15, 36
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},
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{ /* SYS */
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0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
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},
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{ /* MON */
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/* TODO Fix the register mapping for mon, we need r13_mon,
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* r14_mon and spsr_mon
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*/
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0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
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}
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};
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void armv7a_show_fault_registers(struct target *target)
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static void armv7a_show_fault_registers(struct target *target)
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{
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uint32_t dfsr, ifsr, dfar, ifar;
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struct armv7a_common *armv7a = target_to_armv7a(target);
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@ -169,16 +73,14 @@ int armv7a_arch_state(struct target *target)
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}
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LOG_USER("target halted in %s state due to %s, current mode: %s\n"
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"%s: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
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"cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
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"MMU: %s, D-Cache: %s, I-Cache: %s",
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armv7a_state_strings[armv7a->core_state],
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Jim_Nvp_value2name_simple(nvp_target_debug_reason,
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target->debug_reason)->name,
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arm_mode_name(armv4_5->core_mode),
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armv7a_core_reg_list[armv7a_core_reg_map[
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armv7a_mode_to_number(armv4_5->core_mode)][16]],
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buf_get_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
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armv4_5->core_mode, 16).value, 0, 32),
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buf_get_u32(armv4_5->core_cache
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->reg_list[ARMV4_5_CPSR].value, 0, 32),
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buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
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state[armv7a->armv4_5_mmu.mmu_enabled],
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state[armv7a->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
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@ -45,15 +45,6 @@ typedef enum armv7a_state
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ARMV7A_STATE_THUMBEE,
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} armv7a_state_t;
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extern char *armv7a_state_strings[];
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extern int armv7a_core_reg_map[8][17];
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#define ARMV7A_CORE_REG_MODE(cache, mode, num) \
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cache->reg_list[armv7a_core_reg_map[armv7a_mode_to_number(mode)][num]]
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#define ARMV7A_CORE_REG_MODENUM(cache, mode, num) \
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cache->reg_list[armv7a_core_reg_map[mode][num]]
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enum
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{
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ARM_PC = 15,
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@ -102,9 +93,6 @@ struct armv7a_common
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struct armv4_5_mmu_common armv4_5_mmu;
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struct arm armv4_5_common;
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// int (*full_context)(struct target *target);
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// int (*read_core_reg)(struct target *target, int num, enum armv7a_mode mode);
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// int (*write_core_reg)(struct target *target, int num, enum armv7a_mode mode, u32 value);
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int (*read_cp15)(struct target *target,
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uint32_t op1, uint32_t op2,
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uint32_t CRn, uint32_t CRm, uint32_t *value);
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@ -149,44 +137,4 @@ struct reg_cache *armv7a_build_reg_cache(struct target *target,
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int armv7a_register_commands(struct command_context *cmd_ctx);
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int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a);
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/* map psr mode bits to linear number */
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static inline int armv7a_mode_to_number(enum armv7a_mode mode)
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{
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switch (mode)
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{
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case ARMV7A_MODE_USR: return 0; break;
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case ARMV7A_MODE_FIQ: return 1; break;
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case ARMV7A_MODE_IRQ: return 2; break;
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case ARMV7A_MODE_SVC: return 3; break;
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case ARMV7A_MODE_ABT: return 4; break;
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case ARMV7A_MODE_UND: return 5; break;
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case ARMV7A_MODE_SYS: return 6; break;
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case ARMV7A_MODE_MON: return 7; break;
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case ARMV7A_MODE_ANY: return 0; break; /* map MODE_ANY to user mode */
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default:
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LOG_ERROR("invalid mode value encountered, val %d", mode);
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return -1;
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}
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}
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/* map linear number to mode bits */
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static inline enum armv7a_mode armv7a_number_to_mode(int number)
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{
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switch(number)
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{
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case 0: return ARMV7A_MODE_USR; break;
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case 1: return ARMV7A_MODE_FIQ; break;
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case 2: return ARMV7A_MODE_IRQ; break;
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case 3: return ARMV7A_MODE_SVC; break;
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case 4: return ARMV7A_MODE_ABT; break;
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case 5: return ARMV7A_MODE_UND; break;
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case 6: return ARMV7A_MODE_SYS; break;
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case 7: return ARMV7A_MODE_MON; break;
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default:
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LOG_ERROR("mode index out of bounds");
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return ARMV7A_MODE_ANY;
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}
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};
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#endif /* ARMV4_5_H */
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@ -242,16 +242,18 @@ static int cortex_a8_dap_read_coreregister_u32(struct target *target,
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if (reg < 15)
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{
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/* Rn to DCCTX, MCR p14, 0, Rd, c0, c5, 0, 0xEE000E15 */
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/* Rn to DCCTX, "MCR p14, 0, Rn, c0, c5, 0" 0xEE00nE15 */
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cortex_a8_exec_opcode(target, ARMV4_5_MCR(14, 0, reg, 0, 5, 0));
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}
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else if (reg == 15)
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{
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/* "MOV r0, r15"; then move r0 to DCCTX */
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cortex_a8_exec_opcode(target, 0xE1A0000F);
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cortex_a8_exec_opcode(target, ARMV4_5_MCR(14, 0, 0, 0, 5, 0));
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}
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else if (reg == 16)
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{
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/* "MRS r0, CPSR"; then move r0 to DCCTX */
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cortex_a8_exec_opcode(target, ARMV4_5_MRS(0, 0));
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cortex_a8_exec_opcode(target, ARMV4_5_MCR(14, 0, 0, 0, 5, 0));
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}
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@ -480,7 +482,7 @@ static int cortex_a8_resume(struct target *target, int current,
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/* current = 1: continue on current pc, otherwise continue at <address> */
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resume_pc = buf_get_u32(
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ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
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ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
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armv4_5->core_mode, 15).value,
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0, 32);
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if (!current)
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@ -501,12 +503,12 @@ static int cortex_a8_resume(struct target *target, int current,
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resume_pc |= 0x1;
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}
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LOG_DEBUG("resume pc = 0x%08" PRIx32, resume_pc);
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buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
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buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
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armv4_5->core_mode, 15).value,
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0, 32, resume_pc);
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ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
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ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
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armv4_5->core_mode, 15).dirty = 1;
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ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
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ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
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armv4_5->core_mode, 15).valid = 1;
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cortex_a8_restore_context(target);
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@ -627,19 +629,23 @@ static int cortex_a8_debug_entry(struct target *target)
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for (i = 0; i <= ARM_PC; i++)
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{
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buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
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buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
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armv4_5->core_mode, i).value,
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0, 32, regfile[i]);
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ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
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ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
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armv4_5->core_mode, i).valid = 1;
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ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
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ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
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armv4_5->core_mode, i).dirty = 0;
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}
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buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
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/* FIXME for exception states, this caches CPSR as SPSR!! */
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buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
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armv4_5->core_mode, 16).value,
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0, 32, cpsr);
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ARMV7A_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).valid = 1;
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ARMV7A_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).dirty = 0;
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ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
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armv4_5->core_mode, 16).valid = 1;
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ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
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armv4_5->core_mode, 16).dirty = 0;
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/* Fixup PC Resume Address */
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if (armv7a->core_state == ARMV7A_STATE_THUMB)
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@ -652,15 +658,15 @@ static int cortex_a8_debug_entry(struct target *target)
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// ARM state
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regfile[ARM_PC] -= 8;
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}
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buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
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buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
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armv4_5->core_mode, ARM_PC).value,
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0, 32, regfile[ARM_PC]);
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ARMV7A_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0)
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.dirty = ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
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ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0)
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.dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
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armv4_5->core_mode, 0).valid;
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ARMV7A_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15)
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.dirty = ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
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ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15)
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.dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
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armv4_5->core_mode, 15).valid;
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#if 0
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@ -738,13 +744,13 @@ static int cortex_a8_step(struct target *target, int current, uint32_t address,
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/* current = 1: continue on current pc, otherwise continue at <address> */
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if (!current)
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{
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buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
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buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
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armv4_5->core_mode, ARM_PC).value,
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0, 32, address);
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}
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else
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{
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address = buf_get_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
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address = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
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armv4_5->core_mode, ARM_PC).value,
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0, 32);
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}
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@ -756,7 +762,8 @@ static int cortex_a8_step(struct target *target, int current, uint32_t address,
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handle_breakpoints = 1;
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if (handle_breakpoints) {
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breakpoint = breakpoint_find(target,
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buf_get_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
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buf_get_u32(ARMV4_5_CORE_REG_MODE(
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armv4_5->core_cache,
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armv4_5->core_mode, 15).value,
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0, 32));
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if (breakpoint)
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@ -812,10 +819,11 @@ static int cortex_a8_restore_context(struct target *target)
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for (i = 15; i >= 0; i--)
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{
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if (ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
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if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
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armv4_5->core_mode, i).dirty)
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{
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value = buf_get_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
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value = buf_get_u32(ARMV4_5_CORE_REG_MODE(
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armv4_5->core_cache,
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armv4_5->core_mode, i).value,
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0, 32);
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/* TODO Check return values */
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@ -859,13 +867,13 @@ static int cortex_a8_load_core_reg_u32(struct target *target, int num,
|
|||
|
||||
/* Register other than r0 - r14 uses r0 for access */
|
||||
if (num > 14)
|
||||
ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
|
||||
ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
|
||||
armv4_5->core_mode, 0).dirty =
|
||||
ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
|
||||
ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
|
||||
armv4_5->core_mode, 0).valid;
|
||||
ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
|
||||
ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
|
||||
armv4_5->core_mode, 15).dirty =
|
||||
ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
|
||||
ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
|
||||
armv4_5->core_mode, 15).valid;
|
||||
|
||||
return ERROR_OK;
|
||||
|
|
@ -895,9 +903,9 @@ static int cortex_a8_store_core_reg_u32(struct target *target, int num,
|
|||
if (retval != ERROR_OK)
|
||||
{
|
||||
LOG_ERROR("JTAG failure %i", retval);
|
||||
ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
|
||||
ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
|
||||
armv4_5->core_mode, num).dirty =
|
||||
ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
|
||||
ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
|
||||
armv4_5->core_mode, num).valid;
|
||||
return ERROR_JTAG_DEVICE_ERROR;
|
||||
}
|
||||
|
|
@ -920,6 +928,8 @@ static int cortex_a8_read_core_reg(struct target *target, int num,
|
|||
int retval;
|
||||
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
|
||||
|
||||
/* FIXME cortex may not be in "mode" ... */
|
||||
|
||||
cortex_a8_dap_read_coreregister_u32(target, &value, num);
|
||||
|
||||
if ((retval = jtag_execute_queue()) != ERROR_OK)
|
||||
|
|
@ -927,28 +937,30 @@ static int cortex_a8_read_core_reg(struct target *target, int num,
|
|||
return retval;
|
||||
}
|
||||
|
||||
ARMV7A_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
|
||||
ARMV7A_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
|
||||
buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
|
||||
ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
|
||||
ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
|
||||
buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
|
||||
mode, num).value, 0, 32, value);
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
int cortex_a8_write_core_reg(struct target *target, int num,
|
||||
static int cortex_a8_write_core_reg(struct target *target, int num,
|
||||
enum armv4_5_mode mode, uint32_t value)
|
||||
{
|
||||
int retval;
|
||||
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
|
||||
|
||||
/* FIXME cortex may not be in "mode" ... */
|
||||
|
||||
cortex_a8_dap_write_coreregister_u32(target, value, num);
|
||||
if ((retval = jtag_execute_queue()) != ERROR_OK)
|
||||
{
|
||||
return retval;
|
||||
}
|
||||
|
||||
ARMV7A_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
|
||||
ARMV7A_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
|
||||
ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
|
||||
ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue