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armv7a: fix debug messages regarding cache on/off state 

Cache bits are not level specific, remove "l1" from debug message.
Also, fix data/instruction mixup in armv7a_l1_i_cache_sanity_check()

Change-Id: I259665ffe62c7ada5b4f98d3fd907e93662d4091
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3028
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Tested-by: jenkins
__archive__
Matthias Welwarsky 2015-10-16 10:46:35 +02:00 committed by Paul Fertser
parent d17c11759f
commit f3716894c6
1 changed files with 2 additions and 2 deletions
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4
src/target/armv7a_cache.c
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@ -35,7 +35,7 @@ static int armv7a_l1_d_cache_sanity_check(struct target *target)
/* check that cache data is on at target halt */
if (!armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled) {
LOG_DEBUG("l1 data cache is not enabled");
LOG_DEBUG("data cache is not enabled");
return ERROR_TARGET_INVALID;
}
@ -53,7 +53,7 @@ static int armv7a_l1_i_cache_sanity_check(struct target *target)
/* check that cache data is on at target halt */
if (!armv7a->armv7a_mmu.armv7a_cache.i_cache_enabled) {
LOG_DEBUG("l1 data cache is not enabled");
LOG_DEBUG("instruction cache is not enabled");
return ERROR_TARGET_INVALID;
}