Support for Arm VFP v3 registers read/write
This patch adds support in openOCD to read/write Arm vector/floating point registers. This is compatible with Arm vfp v3 target xml in GDB. Please refer to binutils-gdb/gdb/features/arm/arm-vfpv3.xml Change-Id: Id4dd1bddef51c558f1a86300c1a876d159463f18 Signed-off-by: Omair Javaid <omair.javaid@linaro.org> Reviewed-on: http://openocd.zylin.com/4421 Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> Tested-by: jenkinsriscv-compliance-dev
Omair Javaid
Matthias Welwarsky
parent
2830008be0
commit
f18ca510b3
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@ -77,6 +77,43 @@ enum arm_mode {
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ARM_MODE_ANY = -1
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};
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/* VFPv3 internal register numbers mapping to d0:31 */
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enum {
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ARM_VFP_V3_D0 = 51,
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ARM_VFP_V3_D1,
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ARM_VFP_V3_D2,
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ARM_VFP_V3_D3,
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ARM_VFP_V3_D4,
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ARM_VFP_V3_D5,
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ARM_VFP_V3_D6,
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ARM_VFP_V3_D7,
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ARM_VFP_V3_D8,
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ARM_VFP_V3_D9,
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ARM_VFP_V3_D10,
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ARM_VFP_V3_D11,
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ARM_VFP_V3_D12,
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ARM_VFP_V3_D13,
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ARM_VFP_V3_D14,
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ARM_VFP_V3_D15,
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ARM_VFP_V3_D16,
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ARM_VFP_V3_D17,
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ARM_VFP_V3_D18,
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ARM_VFP_V3_D19,
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ARM_VFP_V3_D20,
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ARM_VFP_V3_D21,
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ARM_VFP_V3_D22,
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ARM_VFP_V3_D23,
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ARM_VFP_V3_D24,
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ARM_VFP_V3_D25,
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ARM_VFP_V3_D26,
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ARM_VFP_V3_D27,
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ARM_VFP_V3_D28,
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ARM_VFP_V3_D29,
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ARM_VFP_V3_D30,
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ARM_VFP_V3_D31,
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ARM_VFP_V3_FPSCR,
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};
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const char *arm_mode_name(unsigned psr_mode);
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bool is_arm_mode(unsigned psr_mode);
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@ -89,6 +126,14 @@ enum arm_state {
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ARM_STATE_AARCH64,
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};
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/** ARM vector floating point enabled, if yes which version. */
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enum arm_vfp_version {
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ARM_VFP_DISABLED,
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ARM_VFP_V1,
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ARM_VFP_V2,
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ARM_VFP_V3,
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};
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#define ARM_COMMON_MAGIC 0x0A450A45
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/**
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@ -145,6 +190,9 @@ struct arm {
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/** Flag reporting whether semihosting fileio operation is active. */
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bool semihosting_hit_fileio;
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/** Floating point or VFP version, 0 if disabled. */
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int arm_vfp_version;
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/** Current semihosting operation. */
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int semihosting_op;
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@ -131,6 +131,42 @@ int dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode)
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return retval;
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}
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/* Read 64bit VFP registers */
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static int dpm_read_reg_u64(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
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{
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int retval = ERROR_FAIL;
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uint32_t value_r0, value_r1;
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switch (regnum) {
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case ARM_VFP_V3_D0 ... ARM_VFP_V3_D31:
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/* move from double word register to r0:r1: "vmov r0, r1, vm"
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* then read r0 via dcc
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*/
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retval = dpm->instr_read_data_r0(dpm,
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ARMV4_5_VMOV(1, 1, 0, ((regnum - ARM_VFP_V3_D0) >> 4),
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((regnum - ARM_VFP_V3_D0) & 0xf)), &value_r0);
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/* read r1 via dcc */
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retval = dpm->instr_read_data_dcc(dpm,
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ARMV4_5_MCR(14, 0, 1, 0, 5, 0),
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&value_r1);
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break;
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default:
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break;
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}
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if (retval == ERROR_OK) {
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buf_set_u32(r->value, 0, 32, value_r0);
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buf_set_u32(r->value + 4, 0, 32, value_r1);
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r->valid = true;
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r->dirty = false;
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LOG_DEBUG("READ: %s, %8.8x, %8.8x", r->name,
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(unsigned) value_r0, (unsigned) value_r1);
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}
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return retval;
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}
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/* just read the register -- rely on the core mode being right */
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static int dpm_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
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{
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@ -171,6 +207,14 @@ static int dpm_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
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break;
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}
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break;
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case ARM_VFP_V3_D0 ... ARM_VFP_V3_D31:
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return dpm_read_reg_u64(dpm, r, regnum);
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break;
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case ARM_VFP_V3_FPSCR:
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/* "VMRS r0, FPSCR"; then return via DCC */
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retval = dpm->instr_read_data_r0(dpm,
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ARMV4_5_VMRS(0), &value);
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break;
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default:
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/* 16: "MRS r0, CPSR"; then return via DCC
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* 17: "MRS r0, SPSR"; then return via DCC
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@ -191,6 +235,40 @@ static int dpm_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
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return retval;
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}
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/* Write 64bit VFP registers */
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static int dpm_write_reg_u64(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
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{
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int retval = ERROR_FAIL;
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uint32_t value_r0 = buf_get_u32(r->value, 0, 32);
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uint32_t value_r1 = buf_get_u32(r->value + 4, 0, 32);
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switch (regnum) {
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case ARM_VFP_V3_D0 ... ARM_VFP_V3_D31:
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/* write value_r1 to r1 via dcc */
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retval = dpm->instr_write_data_dcc(dpm,
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ARMV4_5_MRC(14, 0, 1, 0, 5, 0),
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value_r1);
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/* write value_r0 to r0 via dcc then,
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* move to double word register from r0:r1: "vmov vm, r0, r1"
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*/
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retval = dpm->instr_write_data_r0(dpm,
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ARMV4_5_VMOV(0, 1, 0, ((regnum - ARM_VFP_V3_D0) >> 4),
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((regnum - ARM_VFP_V3_D0) & 0xf)), value_r0);
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break;
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default:
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break;
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}
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if (retval == ERROR_OK) {
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r->dirty = false;
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LOG_DEBUG("WRITE: %s, %8.8x, %8.8x", r->name,
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(unsigned) value_r0, (unsigned) value_r1);
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}
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return retval;
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}
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/* just write the register -- rely on the core mode being right */
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static int dpm_write_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
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{
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@ -208,6 +286,14 @@ static int dpm_write_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
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* read r0 from DCC; then "MOV pc, r0" */
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retval = dpm->instr_write_data_r0(dpm, 0xe1a0f000, value);
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break;
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case ARM_VFP_V3_D0 ... ARM_VFP_V3_D31:
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return dpm_write_reg_u64(dpm, r, regnum);
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break;
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case ARM_VFP_V3_FPSCR:
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/* move to r0 from DCC, then "VMSR FPSCR, r0" */
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retval = dpm->instr_write_data_r0(dpm,
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ARMV4_5_VMSR(0), value);
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break;
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default:
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/* 16: read r0 from DCC, then "MSR r0, CPSR_cxsf"
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* 17: read r0 from DCC, then "MSR r0, SPSR_cxsf"
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@ -262,14 +348,16 @@ int arm_dpm_read_current_registers(struct arm_dpm *dpm)
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if (retval != ERROR_OK)
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return retval;
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/* read R0 first (it's used for scratch), then CPSR */
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r = arm->core_cache->reg_list + 0;
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if (!r->valid) {
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retval = dpm_read_reg(dpm, r, 0);
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if (retval != ERROR_OK)
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goto fail;
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/* read R0 and R1 first (it's used for scratch), then CPSR */
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for (unsigned i = 0; i < 2; i++) {
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r = arm->core_cache->reg_list + i;
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if (!r->valid) {
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retval = dpm_read_reg(dpm, r, i);
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if (retval != ERROR_OK)
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goto fail;
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}
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r->dirty = true;
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}
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r->dirty = true;
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retval = dpm->instr_read_data_r0(dpm, ARMV4_5_MRS(0, 0), &cpsr);
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if (retval != ERROR_OK)
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@ -279,7 +367,7 @@ int arm_dpm_read_current_registers(struct arm_dpm *dpm)
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arm_set_cpsr(arm, cpsr);
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/* REVISIT we can probably avoid reading R1..R14, saving time... */
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for (unsigned i = 1; i < 16; i++) {
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for (unsigned i = 2; i < 16; i++) {
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r = arm_reg_current(arm, i);
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if (r->valid)
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continue;
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@ -412,8 +500,8 @@ int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
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did_write = false;
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/* check everything except our scratch register R0 */
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for (unsigned i = 1; i < cache->num_regs; i++) {
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/* check everything except our scratch registers R0 and R1 */
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for (unsigned i = 2; i < cache->num_regs; i++) {
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struct arm_reg *r;
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unsigned regnum;
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@ -540,6 +628,7 @@ static enum arm_mode dpm_mapmode(struct arm *arm,
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/* r13/sp, and r14/lr are always shadowed */
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case 13:
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case 14:
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case ARM_VFP_V3_D0 ... ARM_VFP_V3_FPSCR:
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return mode;
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default:
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LOG_WARNING("invalid register #%u", num);
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@ -561,7 +650,8 @@ static int arm_dpm_read_core_reg(struct target *target, struct reg *r,
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struct arm_dpm *dpm = target_to_arm(target)->dpm;
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int retval;
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if (regnum < 0 || regnum > 16)
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if (regnum < 0 || (regnum > 16 && regnum < ARM_VFP_V3_D0) ||
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(regnum > ARM_VFP_V3_FPSCR))
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return ERROR_COMMAND_SYNTAX_ERROR;
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if (regnum == 16) {
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@ -604,7 +694,8 @@ static int arm_dpm_write_core_reg(struct target *target, struct reg *r,
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int retval;
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if (regnum < 0 || regnum > 16)
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if (regnum < 0 || (regnum > 16 && regnum < ARM_VFP_V3_D0) ||
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(regnum > ARM_VFP_V3_FPSCR))
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return ERROR_COMMAND_SYNTAX_ERROR;
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if (regnum == 16) {
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@ -132,6 +132,30 @@
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*/
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#define ARMV4_5_BX(Rm) (0xe12fff10 | (Rm))
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/* Copies two words from two ARM core registers
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* into a doubleword extension register, or
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* from a doubleword extension register to two ARM core registers.
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* See Armv7-A arch reference manual section A8.8.345
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* Rt: Arm core register 1
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* Rt2: Arm core register 2
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* Vm: The doubleword extension register
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* M: m = UInt(M:Vm);
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* op: to_arm_registers = (op == ‘1’);
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*/
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#define ARMV4_5_VMOV(op, Rt2, Rt, M, Vm) \
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(0xec400b10 | ((op) << 20) | ((Rt2) << 16) | \
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((Rt) << 12) | ((M) << 5) | (Vm))
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/* Moves the value of the FPSCR to an ARM core register
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* Rt: Arm core register
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*/
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#define ARMV4_5_VMRS(Rt) (0xeef10a10 | ((Rt) << 12))
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/* Moves the value of an ARM core register to the FPSCR.
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* Rt: Arm core register
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*/
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#define ARMV4_5_VMSR(Rt) (0xeee10a10 | ((Rt) << 12))
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/* Store data from coprocessor to consecutive memory
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* See Armv7-A arch doc section A8.6.187
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* P: 1=index mode (offset from Rn)
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@ -340,6 +340,50 @@ static const struct {
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};
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static const struct {
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unsigned int id;
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const char *name;
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uint32_t bits;
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enum arm_mode mode;
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enum reg_type type;
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const char *group;
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const char *feature;
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} arm_vfp_v3_regs[] = {
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{ ARM_VFP_V3_D0, "d0", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
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{ ARM_VFP_V3_D1, "d1", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
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{ ARM_VFP_V3_D2, "d2", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
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{ ARM_VFP_V3_D3, "d3", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
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{ ARM_VFP_V3_D4, "d4", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
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{ ARM_VFP_V3_D5, "d5", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
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{ ARM_VFP_V3_D6, "d6", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
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{ ARM_VFP_V3_D7, "d7", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
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{ ARM_VFP_V3_D8, "d8", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
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{ ARM_VFP_V3_D9, "d9", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
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{ ARM_VFP_V3_D10, "d10", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
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{ ARM_VFP_V3_D11, "d11", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
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{ ARM_VFP_V3_D12, "d12", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
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{ ARM_VFP_V3_D13, "d13", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
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{ ARM_VFP_V3_D14, "d14", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
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{ ARM_VFP_V3_D15, "d15", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
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{ ARM_VFP_V3_D16, "d16", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
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{ ARM_VFP_V3_D17, "d17", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
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{ ARM_VFP_V3_D18, "d18", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
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{ ARM_VFP_V3_D19, "d19", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
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{ ARM_VFP_V3_D20, "d20", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
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{ ARM_VFP_V3_D21, "d21", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
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{ ARM_VFP_V3_D22, "d22", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
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{ ARM_VFP_V3_D23, "d23", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
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{ ARM_VFP_V3_D24, "d24", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
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{ ARM_VFP_V3_D25, "d25", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
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{ ARM_VFP_V3_D26, "d26", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
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{ ARM_VFP_V3_D27, "d27", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
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{ ARM_VFP_V3_D28, "d28", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
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{ ARM_VFP_V3_D29, "d29", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
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{ ARM_VFP_V3_D30, "d30", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
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{ ARM_VFP_V3_D31, "d31", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
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{ ARM_VFP_V3_FPSCR, "fpscr", 32, ARM_MODE_ANY, REG_TYPE_INT, "float", "org.gnu.gdb.arm.vfp"},
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};
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/* map core mode (USR, FIQ, ...) and register number to
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* indices into the register cache
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*/
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@ -567,6 +611,10 @@ static int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf)
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}
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} else {
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buf_set_u32(reg->value, 0, 32, value);
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if (reg->size == 64) {
|
||||
value = buf_get_u32(buf + 4, 0, 32);
|
||||
buf_set_u32(reg->value + 4, 0, 32, value);
|
||||
}
|
||||
reg->valid = 1;
|
||||
}
|
||||
reg->dirty = 1;
|
||||
|
|
@ -582,6 +630,10 @@ static const struct reg_arch_type arm_reg_type = {
|
|||
struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm)
|
||||
{
|
||||
int num_regs = ARRAY_SIZE(arm_core_regs);
|
||||
int num_core_regs = num_regs;
|
||||
if (arm->arm_vfp_version == ARM_VFP_V3)
|
||||
num_regs += ARRAY_SIZE(arm_vfp_v3_regs);
|
||||
|
||||
struct reg_cache *cache = malloc(sizeof(struct reg_cache));
|
||||
struct reg *reg_list = calloc(num_regs, sizeof(struct reg));
|
||||
struct arm_reg *reg_arch_info = calloc(num_regs, sizeof(struct arm_reg));
|
||||
|
|
@ -599,7 +651,7 @@ struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm)
|
|||
cache->reg_list = reg_list;
|
||||
cache->num_regs = 0;
|
||||
|
||||
for (i = 0; i < num_regs; i++) {
|
||||
for (i = 0; i < num_core_regs; i++) {
|
||||
/* Skip registers this core doesn't expose */
|
||||
if (arm_core_regs[i].mode == ARM_MODE_MON
|
||||
&& arm->core_type != ARM_MODE_MON)
|
||||
|
|
@ -651,9 +703,38 @@ struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm)
|
|||
cache->num_regs++;
|
||||
}
|
||||
|
||||
int j;
|
||||
for (i = num_core_regs, j = 0; i < num_regs; i++, j++) {
|
||||
reg_arch_info[i].num = arm_vfp_v3_regs[j].id;
|
||||
reg_arch_info[i].mode = arm_vfp_v3_regs[j].mode;
|
||||
reg_arch_info[i].target = target;
|
||||
reg_arch_info[i].arm = arm;
|
||||
|
||||
reg_list[i].name = arm_vfp_v3_regs[j].name;
|
||||
reg_list[i].number = arm_vfp_v3_regs[j].id;
|
||||
reg_list[i].size = arm_vfp_v3_regs[j].bits;
|
||||
reg_list[i].value = reg_arch_info[i].value;
|
||||
reg_list[i].type = &arm_reg_type;
|
||||
reg_list[i].arch_info = ®_arch_info[i];
|
||||
reg_list[i].exist = true;
|
||||
|
||||
reg_list[i].caller_save = false;
|
||||
|
||||
reg_list[i].reg_data_type = malloc(sizeof(struct reg_data_type));
|
||||
reg_list[i].reg_data_type->type = arm_vfp_v3_regs[j].type;
|
||||
|
||||
reg_list[i].feature = malloc(sizeof(struct reg_feature));
|
||||
reg_list[i].feature->name = arm_vfp_v3_regs[j].feature;
|
||||
|
||||
reg_list[i].group = arm_vfp_v3_regs[j].group;
|
||||
|
||||
cache->num_regs++;
|
||||
}
|
||||
|
||||
arm->pc = reg_list + 15;
|
||||
arm->cpsr = reg_list + ARMV4_5_CPSR;
|
||||
arm->core_cache = cache;
|
||||
|
||||
return cache;
|
||||
}
|
||||
|
||||
|
|
@ -1229,6 +1310,10 @@ int arm_get_gdb_reg_list(struct target *target,
|
|||
|
||||
case REG_CLASS_ALL:
|
||||
*reg_list_size = (arm->core_type != ARM_MODE_MON ? 48 : 51);
|
||||
unsigned int list_size_core = *reg_list_size;
|
||||
if (arm->arm_vfp_version == ARM_VFP_V3)
|
||||
*reg_list_size += 33;
|
||||
|
||||
*reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
|
||||
|
||||
for (i = 0; i < 16; i++)
|
||||
|
|
@ -1249,6 +1334,12 @@ int arm_get_gdb_reg_list(struct target *target,
|
|||
(*reg_list)[24] = &arm_gdb_dummy_fps_reg;
|
||||
(*reg_list)[24]->size = 0;
|
||||
|
||||
if (arm->arm_vfp_version == ARM_VFP_V3) {
|
||||
unsigned int num_core_regs = ARRAY_SIZE(arm_core_regs);
|
||||
for (i = 0; i < 33; i++)
|
||||
(*reg_list)[list_size_core + i] = &(arm->core_cache->reg_list[num_core_regs + i]);
|
||||
}
|
||||
|
||||
return ERROR_OK;
|
||||
break;
|
||||
|
||||
|
|
|
|||
|
|
@ -3178,6 +3178,8 @@ static int cortex_a_target_create(struct target *target, Jim_Interp *interp)
|
|||
|
||||
cortex_a->armv7a_common.is_armv7r = false;
|
||||
|
||||
cortex_a->armv7a_common.arm.arm_vfp_version = ARM_VFP_V3;
|
||||
|
||||
return cortex_a_init_arch_info(target, cortex_a, target->tap);
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue