psoc5lp: Add EEPROM flash driver
Tested on CY8CKIT-059. Change-Id: Ib02262e8eebf0df3d29492b8a7daa65b262da580 Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/3433 Tested-by: jenkinsriscv-compliance
Andreas Färber
Tomas Vanek
parent
2d5f2ede55
commit
f1427cca3c
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@ -6168,6 +6168,17 @@ and all row latches in all flash arrays on the device.
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@end deffn
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@end deffn
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@deffn {Flash Driver} psoc5lp_eeprom
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All members of the PSoC 5LP microcontroller family from Cypress
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include internal EEPROM and use ARM Cortex-M3 cores.
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The driver probes for a number of these chips and autoconfigures itself,
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apart from the base address.
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@example
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flash bank $_CHIPNAME.eeprom psoc5lp_eeprom 0x40008000 0 0 0 $_TARGETNAME
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@end example
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@end deffn
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@deffn {Flash Driver} psoc6
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Supports PSoC6 (CY8C6xxx) family of Cypress microcontrollers.
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PSoC6 is a dual-core device with CM0+ and CM4 cores. Both cores share
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@ -57,6 +57,7 @@ extern struct flash_driver ocl_flash;
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extern struct flash_driver pic32mx_flash;
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extern struct flash_driver psoc4_flash;
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extern struct flash_driver psoc5lp_flash;
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extern struct flash_driver psoc5lp_eeprom_flash;
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extern struct flash_driver psoc6_flash;
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extern struct flash_driver sim3x_flash;
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extern struct flash_driver stellaris_flash;
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@ -117,6 +118,7 @@ static struct flash_driver *flash_drivers[] = {
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&pic32mx_flash,
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&psoc4_flash,
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&psoc5lp_flash,
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&psoc5lp_eeprom_flash,
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&psoc6_flash,
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&sim3x_flash,
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&stellaris_flash,
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@ -26,6 +26,7 @@
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#include <target/armv7m.h>
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#define PM_ACT_CFG0 0x400043A0
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#define PM_ACT_CFG12 0x400043AC
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#define SPC_CPU_DATA 0x40004720
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#define SPC_SR 0x40004722
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#define PHUB_CH0_BASIC_CFG 0x40007010
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@ -44,6 +45,8 @@
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#define PHUB_TDMEM1_ORIG_TD1 0x4000780C
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#define PANTHER_DEVICE_ID 0x4008001C
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#define PM_ACT_CFG12_EN_EE (1 << 4)
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#define SPC_KEY1 0xB6
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#define SPC_KEY2 0xD3
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@ -96,6 +99,9 @@
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#define ROWS_PER_BLOCK 256
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#define BLOCK_SIZE (ROWS_PER_BLOCK * ROW_SIZE)
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#define SECTORS_PER_BLOCK (BLOCK_SIZE / SECTOR_SIZE)
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#define EEPROM_ROW_SIZE 16
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#define EEPROM_SECTOR_SIZE (ROWS_PER_SECTOR * EEPROM_ROW_SIZE)
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#define EEPROM_BLOCK_SIZE (ROWS_PER_BLOCK * EEPROM_ROW_SIZE)
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#define PART_NUMBER_LEN (17 + 1)
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@ -353,6 +359,32 @@ static int psoc5lp_spc_busy_wait_idle(struct target *target)
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return ERROR_FLASH_OPERATION_FAILED;
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}
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static int psoc5lp_spc_load_row(struct target *target,
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uint8_t array_id, const uint8_t *data, unsigned row_size)
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{
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unsigned i;
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int retval;
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retval = psoc5lp_spc_write_opcode(target, SPC_LOAD_ROW);
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if (retval != ERROR_OK)
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return retval;
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retval = target_write_u8(target, SPC_CPU_DATA, array_id);
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if (retval != ERROR_OK)
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return retval;
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for (i = 0; i < row_size; i++) {
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retval = target_write_u8(target, SPC_CPU_DATA, data[i]);
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if (retval != ERROR_OK)
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return retval;
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}
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retval = psoc5lp_spc_busy_wait_idle(target);
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if (retval != ERROR_OK)
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return retval;
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return ERROR_OK;
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}
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static int psoc5lp_spc_read_byte(struct target *target,
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uint8_t array_id, uint8_t offset, uint8_t *data)
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{
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@ -383,6 +415,37 @@ static int psoc5lp_spc_read_byte(struct target *target,
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return ERROR_OK;
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}
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static int psoc5lp_spc_write_row(struct target *target,
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uint8_t array_id, uint16_t row_id, const uint8_t *temp)
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{
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int retval;
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retval = psoc5lp_spc_write_opcode(target, SPC_WRITE_ROW);
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if (retval != ERROR_OK)
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return retval;
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retval = target_write_u8(target, SPC_CPU_DATA, array_id);
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if (retval != ERROR_OK)
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return retval;
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retval = target_write_u8(target, SPC_CPU_DATA, row_id >> 8);
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if (retval != ERROR_OK)
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return retval;
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retval = target_write_u8(target, SPC_CPU_DATA, row_id & 0xff);
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if (retval != ERROR_OK)
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return retval;
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retval = target_write_u8(target, SPC_CPU_DATA, temp[0]);
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if (retval != ERROR_OK)
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return retval;
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retval = target_write_u8(target, SPC_CPU_DATA, temp[1]);
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if (retval != ERROR_OK)
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return retval;
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retval = psoc5lp_spc_busy_wait_idle(target);
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if (retval != ERROR_OK)
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return retval;
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return ERROR_OK;
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}
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static int psoc5lp_spc_erase_sector(struct target *target,
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uint8_t array_id, uint8_t row_id)
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{
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@ -482,6 +545,214 @@ static int psoc5lp_spc_get_temp(struct target *target, uint8_t samples,
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return ERROR_OK;
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}
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/*
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* EEPROM
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*/
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struct psoc5lp_eeprom_flash_bank {
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bool probed;
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const struct psoc5lp_device *device;
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};
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static int psoc5lp_eeprom_erase(struct flash_bank *bank, int first, int last)
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{
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int i, retval;
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for (i = first; i <= last; i++) {
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retval = psoc5lp_spc_erase_sector(bank->target,
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SPC_ARRAY_EEPROM, i);
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if (retval != ERROR_OK)
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return retval;
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}
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return ERROR_OK;
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}
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static int psoc5lp_eeprom_write(struct flash_bank *bank,
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const uint8_t *buffer, uint32_t offset, uint32_t byte_count)
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{
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struct target *target = bank->target;
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uint8_t temp[2];
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unsigned row;
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int retval;
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if (offset % EEPROM_ROW_SIZE != 0) {
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LOG_ERROR("Writes must be row-aligned, got offset 0x%08" PRIx32,
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offset);
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return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
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}
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retval = psoc5lp_spc_get_temp(target, 3, temp);
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if (retval != ERROR_OK) {
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LOG_ERROR("Unable to read Die temperature");
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return retval;
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}
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LOG_DEBUG("Get_Temp: sign 0x%02" PRIx8 ", magnitude 0x%02" PRIx8,
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temp[0], temp[1]);
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for (row = offset / EEPROM_ROW_SIZE; byte_count >= EEPROM_ROW_SIZE; row++) {
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retval = psoc5lp_spc_load_row(target, SPC_ARRAY_EEPROM,
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buffer, EEPROM_ROW_SIZE);
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if (retval != ERROR_OK)
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return retval;
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retval = psoc5lp_spc_write_row(target, SPC_ARRAY_EEPROM,
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row, temp);
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if (retval != ERROR_OK)
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return retval;
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buffer += EEPROM_ROW_SIZE;
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byte_count -= EEPROM_ROW_SIZE;
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offset += EEPROM_ROW_SIZE;
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}
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if (byte_count > 0) {
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uint8_t buf[EEPROM_ROW_SIZE];
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memcpy(buf, buffer, byte_count);
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memset(buf + byte_count, bank->default_padded_value,
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EEPROM_ROW_SIZE - byte_count);
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LOG_DEBUG("Padding %d bytes", EEPROM_ROW_SIZE - byte_count);
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retval = psoc5lp_spc_load_row(target, SPC_ARRAY_EEPROM,
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buf, EEPROM_ROW_SIZE);
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if (retval != ERROR_OK)
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return retval;
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retval = psoc5lp_spc_write_row(target, SPC_ARRAY_EEPROM,
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row, temp);
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if (retval != ERROR_OK)
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return retval;
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}
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return ERROR_OK;
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}
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static int psoc5lp_eeprom_protect_check(struct flash_bank *bank)
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{
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int i;
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for (i = 0; i < bank->num_sectors; i++)
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bank->sectors[i].is_protected = -1;
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return ERROR_OK;
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}
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static int psoc5lp_eeprom_get_info_command(struct flash_bank *bank, char *buf, int buf_size)
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{
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struct psoc5lp_eeprom_flash_bank *psoc_eeprom_bank = bank->driver_priv;
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char part_number[PART_NUMBER_LEN];
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psoc5lp_get_part_number(psoc_eeprom_bank->device, part_number);
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snprintf(buf, buf_size, "%s", part_number);
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return ERROR_OK;
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}
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static int psoc5lp_eeprom_probe(struct flash_bank *bank)
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{
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struct psoc5lp_eeprom_flash_bank *psoc_eeprom_bank = bank->driver_priv;
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uint32_t flash_addr = bank->base;
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uint32_t val;
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int i, retval;
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if (psoc_eeprom_bank->probed)
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return ERROR_OK;
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if (bank->target->state != TARGET_HALTED) {
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LOG_ERROR("Target not halted");
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return ERROR_TARGET_NOT_HALTED;
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}
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retval = psoc5lp_find_device(bank->target, &psoc_eeprom_bank->device);
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if (retval != ERROR_OK)
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return retval;
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retval = target_read_u32(bank->target, PM_ACT_CFG12, &val);
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if (retval != ERROR_OK)
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return retval;
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if (!(val & PM_ACT_CFG12_EN_EE)) {
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val |= PM_ACT_CFG12_EN_EE;
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retval = target_write_u32(bank->target, PM_ACT_CFG12, val);
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if (retval != ERROR_OK)
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return retval;
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}
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bank->size = psoc_eeprom_bank->device->eeprom_kb * 1024;
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bank->num_sectors = DIV_ROUND_UP(bank->size, EEPROM_SECTOR_SIZE);
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bank->sectors = calloc(bank->num_sectors,
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sizeof(struct flash_sector));
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for (i = 0; i < bank->num_sectors; i++) {
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bank->sectors[i].size = EEPROM_SECTOR_SIZE;
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bank->sectors[i].offset = flash_addr - bank->base;
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bank->sectors[i].is_erased = -1;
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bank->sectors[i].is_protected = -1;
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flash_addr += bank->sectors[i].size;
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}
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bank->default_padded_value = bank->erased_value = 0x00;
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psoc_eeprom_bank->probed = true;
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return ERROR_OK;
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}
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static int psoc5lp_eeprom_auto_probe(struct flash_bank *bank)
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{
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struct psoc5lp_eeprom_flash_bank *psoc_eeprom_bank = bank->driver_priv;
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if (psoc_eeprom_bank->probed)
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return ERROR_OK;
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return psoc5lp_eeprom_probe(bank);
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}
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FLASH_BANK_COMMAND_HANDLER(psoc5lp_eeprom_flash_bank_command)
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{
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struct psoc5lp_eeprom_flash_bank *psoc_eeprom_bank;
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psoc_eeprom_bank = malloc(sizeof(struct psoc5lp_eeprom_flash_bank));
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if (!psoc_eeprom_bank)
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return ERROR_FLASH_OPERATION_FAILED;
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psoc_eeprom_bank->probed = false;
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psoc_eeprom_bank->device = NULL;
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bank->driver_priv = psoc_eeprom_bank;
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return ERROR_OK;
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}
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static const struct command_registration psoc5lp_eeprom_exec_command_handlers[] = {
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COMMAND_REGISTRATION_DONE
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};
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static const struct command_registration psoc5lp_eeprom_command_handlers[] = {
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{
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.name = "psoc5lp_eeprom",
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.mode = COMMAND_ANY,
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.help = "PSoC 5LP EEPROM command group",
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.usage = "",
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.chain = psoc5lp_eeprom_exec_command_handlers,
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},
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COMMAND_REGISTRATION_DONE
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};
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struct flash_driver psoc5lp_eeprom_flash = {
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.name = "psoc5lp_eeprom",
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.commands = psoc5lp_eeprom_command_handlers,
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.flash_bank_command = psoc5lp_eeprom_flash_bank_command,
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.info = psoc5lp_eeprom_get_info_command,
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.probe = psoc5lp_eeprom_probe,
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.auto_probe = psoc5lp_eeprom_auto_probe,
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.protect_check = psoc5lp_eeprom_protect_check,
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.read = default_flash_read,
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.erase = psoc5lp_eeprom_erase,
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.erase_check = default_flash_blank_check,
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.write = psoc5lp_eeprom_write,
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};
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/*
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* Program Flash
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*/
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@ -57,6 +57,7 @@ $_TARGETNAME configure -event reset-init {
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME psoc5lp 0x00000000 0 0 0 $_TARGETNAME
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flash bank $_CHIPNAME.eeprom psoc5lp_eeprom 0x40008000 0 0 0 $_TARGETNAME
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if {![using_hla]} {
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cortex_m reset_config sysresetreq
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