From f132fcf636361009b4125827351ef01556d49b31 Mon Sep 17 00:00:00 2001 From: Paul Fertser Date: Mon, 30 Sep 2013 13:31:57 +0400 Subject: [PATCH] Clean up many C99 integer types format specifiers This eliminates most of the warnings reported when building for arm-none-eabi (newlib). Hsiangkai, there're many similar warnings left in your nds32 files, I didn't have the nerve to clean them all, probably you could pick it up. Change-Id: Id3bbe2ed2e3f1396290e55bea4c45068165a4810 Signed-off-by: Paul Fertser Reviewed-on: http://openocd.zylin.com/1674 Tested-by: jenkins Reviewed-by: Spencer Oliver --- src/flash/nand/lpc32xx.c | 10 +++++----- src/flash/nor/at91sam3.c | 14 +++++++------- src/flash/nor/at91sam4.c | 14 +++++++------- src/flash/nor/cfi.c | 2 +- src/flash/nor/core.c | 2 +- src/flash/nor/efm32.c | 12 ++++++------ src/flash/nor/fm3.c | 4 ++-- src/flash/nor/kinetis.c | 18 +++++++++--------- src/flash/nor/lpc2000.c | 2 +- src/flash/nor/lpcspifi.c | 6 +++--- src/flash/nor/nuc1x.c | 6 +++--- src/flash/nor/stm32f2x.c | 6 +++--- src/flash/nor/stm32lx.c | 7 ++++--- src/flash/nor/stmsmi.c | 2 +- src/flash/nor/tcl.c | 10 +++++----- src/target/adi_v5_swd.c | 4 ++-- src/target/arm7_9_common.c | 10 +++++----- src/target/arm946e.c | 5 +++-- src/target/arm_adi_v5.c | 14 +++++++------- src/target/arm_adi_v5.h | 4 ++-- src/target/armv7a.c | 22 +++++++++++----------- src/target/avr32_ap7k.c | 2 +- src/target/breakpoints.c | 16 ++++++++-------- src/target/cortex_a.c | 24 ++++++++++++------------ src/target/cortex_m.c | 8 ++++---- src/target/dsp563xx.c | 12 ++++++------ src/target/dsp5680xx.c | 12 ++++++------ src/target/hla_target.c | 12 ++++++------ src/target/mips32.c | 2 +- src/target/mips32_pracc.c | 5 +++-- src/target/mips_m4k.c | 20 ++++++++++---------- src/target/nds32.c | 18 +++++++++--------- src/target/nds32_cmd.c | 4 ++-- src/target/nds32_reg.c | 2 +- src/target/target.c | 10 +++++----- src/target/xscale.c | 2 +- 36 files changed, 163 insertions(+), 160 deletions(-) diff --git a/src/flash/nand/lpc32xx.c b/src/flash/nand/lpc32xx.c index 1776b309e..38c7e3350 100644 --- a/src/flash/nand/lpc32xx.c +++ b/src/flash/nand/lpc32xx.c @@ -1040,8 +1040,8 @@ static int lpc32xx_write_page_slc(struct nand_device *nand, int retval; uint32_t target_mem_base; - LOG_DEBUG("SLC write page %x data=%d, oob=%d, " - "data_size=%d, oob_size=%d", + LOG_DEBUG("SLC write page %" PRIx32 " data=%d, oob=%d, " + "data_size=%" PRIu32 ", oob_size=%" PRIu32, page, data != 0, oob != 0, data_size, oob_size); target_mem_base = pworking_area->address; @@ -1451,7 +1451,7 @@ static int lpc32xx_read_page_slc(struct nand_device *nand, int retval; uint32_t target_mem_base; - LOG_DEBUG("SLC read page %x data=%d, oob=%d", + LOG_DEBUG("SLC read page %" PRIx32 " data=%" PRIu32 ", oob=%" PRIu32, page, data_size, oob_size); target_mem_base = pworking_area->address; @@ -1558,7 +1558,7 @@ static int lpc32xx_read_page_slc(struct nand_device *nand, retval = nand_correct_data(nand, data + 256*i, &fecc[i * 3], &ecc[i * 3]); if (retval > 0) - LOG_WARNING("error detected and corrected: %d/%d", + LOG_WARNING("error detected and corrected: %" PRIu32 "/%d", page, i); if (retval < 0) break; @@ -1566,7 +1566,7 @@ static int lpc32xx_read_page_slc(struct nand_device *nand, if (i == ecc_count) retval = ERROR_OK; else { - LOG_ERROR("uncorrectable error detected: %d/%d", page, i); + LOG_ERROR("uncorrectable error detected: %" PRIu32 "/%d", page, i); retval = ERROR_NAND_OPERATION_FAILED; } return retval; diff --git a/src/flash/nor/at91sam3.c b/src/flash/nor/at91sam3.c index 6fe71bfb9..fdae96457 100644 --- a/src/flash/nor/at91sam3.c +++ b/src/flash/nor/at91sam3.c @@ -2333,7 +2333,7 @@ static uint32_t sam3_reg_fieldname(struct sam3_chip *pChip, } /* show the basics */ - LOG_USER_N("\t%*s: %*d [0x%0*x] ", + LOG_USER_N("\t%*s: %*" PRIu32 " [0x%0*" PRIx32 "] ", REG_NAME_WIDTH, regname, dwidth, v, hwidth, v); @@ -2558,10 +2558,10 @@ static void sam3_explain_ckgr_mcfr(struct sam3_chip *pChip) v = (v * pChip->cfg.slow_freq) / 16; pChip->cfg.mainosc_freq = v; - LOG_USER("(%3.03f Mhz (%d.%03dkhz slowclk)", + LOG_USER("(%3.03f Mhz (%" PRIu32 ".%03" PRIu32 "khz slowclk)", _tomhz(v), - pChip->cfg.slow_freq / 1000, - pChip->cfg.slow_freq % 1000); + (uint32_t)(pChip->cfg.slow_freq / 1000), + (uint32_t)(pChip->cfg.slow_freq % 1000)); } static void sam3_explain_ckgr_plla(struct sam3_chip *pChip) @@ -2831,7 +2831,7 @@ static int sam3_GetInfo(struct sam3_chip *pChip) /* display all regs */ LOG_DEBUG("Start: %s", pReg->name); regval = *sam3_get_reg_ptr(&(pChip->cfg), pReg); - LOG_USER("%*s: [0x%08x] -> 0x%08x", + LOG_USER("%*s: [0x%08" PRIx32 "] -> 0x%08" PRIx32, REG_NAME_WIDTH, pReg->name, pReg->address, @@ -2847,7 +2847,7 @@ static int sam3_GetInfo(struct sam3_chip *pChip) LOG_USER(" cpu-freq: %3.03f MHz", _tomhz(pChip->cfg.cpu_freq)); LOG_USER("mclk-freq: %3.03f MHz", _tomhz(pChip->cfg.mclk_freq)); - LOG_USER(" UniqueId: 0x%08x 0x%08x 0x%08x 0x%08x", + LOG_USER(" UniqueId: 0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08" PRIx32, pChip->cfg.unique_id[0], pChip->cfg.unique_id[1], pChip->cfg.unique_id[2], @@ -3002,7 +3002,7 @@ static int sam3_GetDetails(struct sam3_bank_private *pPrivate) LOG_ERROR("SAM3 ChipID 0x%08x not found in table (perhaps you can ID this chip?)", (unsigned int)(pPrivate->pChip->cfg.CHIPID_CIDR)); /* Help the victim, print details about the chip */ - LOG_INFO("SAM3 CHIPID_CIDR: 0x%08x decodes as follows", + LOG_INFO("SAM3 CHIPID_CIDR: 0x%08" PRIx32 " decodes as follows", pPrivate->pChip->cfg.CHIPID_CIDR); sam3_explain_chipid_cidr(pPrivate->pChip); return ERROR_FAIL; diff --git a/src/flash/nor/at91sam4.c b/src/flash/nor/at91sam4.c index 6c8b71e2f..f34ca4f6b 100644 --- a/src/flash/nor/at91sam4.c +++ b/src/flash/nor/at91sam4.c @@ -1002,7 +1002,7 @@ static uint32_t sam4_reg_fieldname(struct sam4_chip *pChip, } /* show the basics */ - LOG_USER_N("\t%*s: %*d [0x%0*x] ", + LOG_USER_N("\t%*s: %*" PRId32 " [0x%0*" PRIx32 "] ", REG_NAME_WIDTH, regname, dwidth, v, hwidth, v); @@ -1227,10 +1227,10 @@ static void sam4_explain_ckgr_mcfr(struct sam4_chip *pChip) v = (v * pChip->cfg.slow_freq) / 16; pChip->cfg.mainosc_freq = v; - LOG_USER("(%3.03f Mhz (%d.%03dkhz slowclk)", + LOG_USER("(%3.03f Mhz (%" PRIu32 ".%03" PRIu32 "khz slowclk)", _tomhz(v), - pChip->cfg.slow_freq / 1000, - pChip->cfg.slow_freq % 1000); + (uint32_t)(pChip->cfg.slow_freq / 1000), + (uint32_t)(pChip->cfg.slow_freq % 1000)); } static void sam4_explain_ckgr_plla(struct sam4_chip *pChip) @@ -1479,7 +1479,7 @@ static int sam4_GetInfo(struct sam4_chip *pChip) /* display all regs */ LOG_DEBUG("Start: %s", pReg->name); regval = *sam4_get_reg_ptr(&(pChip->cfg), pReg); - LOG_USER("%*s: [0x%08x] -> 0x%08x", + LOG_USER("%*s: [0x%08" PRIx32 "] -> 0x%08" PRIx32, REG_NAME_WIDTH, pReg->name, pReg->address, @@ -1495,7 +1495,7 @@ static int sam4_GetInfo(struct sam4_chip *pChip) LOG_USER(" cpu-freq: %3.03f MHz", _tomhz(pChip->cfg.cpu_freq)); LOG_USER("mclk-freq: %3.03f MHz", _tomhz(pChip->cfg.mclk_freq)); - LOG_USER(" UniqueId: 0x%08x 0x%08x 0x%08x 0x%08x", + LOG_USER(" UniqueId: 0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08"PRIx32, pChip->cfg.unique_id[0], pChip->cfg.unique_id[1], pChip->cfg.unique_id[2], @@ -1619,7 +1619,7 @@ static int sam4_GetDetails(struct sam4_bank_private *pPrivate) LOG_ERROR("SAM4 ChipID 0x%08x not found in table (perhaps you can ID this chip?)", (unsigned int)(pPrivate->pChip->cfg.CHIPID_CIDR)); /* Help the victim, print details about the chip */ - LOG_INFO("SAM4 CHIPID_CIDR: 0x%08x decodes as follows", + LOG_INFO("SAM4 CHIPID_CIDR: 0x%08" PRIx32 " decodes as follows", pPrivate->pChip->cfg.CHIPID_CIDR); sam4_explain_chipid_cidr(pPrivate->pChip); return ERROR_FAIL; diff --git a/src/flash/nor/cfi.c b/src/flash/nor/cfi.c index c443de2dd..2ade84a85 100644 --- a/src/flash/nor/cfi.c +++ b/src/flash/nor/cfi.c @@ -2307,7 +2307,7 @@ static int cfi_read(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, u } if (count) { - LOG_INFO("Fixup %d unaligned read tail bytes", count); + LOG_INFO("Fixup %" PRIu32 " unaligned read tail bytes", count); /* read a complete word from flash */ retval = target_read_memory(target, read_p, bank->bus_width, 1, current_word); diff --git a/src/flash/nor/core.c b/src/flash/nor/core.c index e61b30326..cc2ecac08 100644 --- a/src/flash/nor/core.c +++ b/src/flash/nor/core.c @@ -595,7 +595,7 @@ int flash_write_unlock(struct target *target, struct image *image, if (retval != ERROR_OK) goto done; if (c == NULL) { - LOG_WARNING("no flash bank found for address %x", run_address); + LOG_WARNING("no flash bank found for address %" PRIx32, run_address); section++; /* and skip it */ section_offset = 0; continue; diff --git a/src/flash/nor/efm32.c b/src/flash/nor/efm32.c index be9f8eea0..eab113331 100644 --- a/src/flash/nor/efm32.c +++ b/src/flash/nor/efm32.c @@ -292,7 +292,7 @@ static int efm32x_erase_page(struct flash_bank *bank, uint32_t addr) int ret = 0; uint32_t status = 0; - LOG_DEBUG("erasing flash page at 0x%08x", addr); + LOG_DEBUG("erasing flash page at 0x%08" PRIx32, addr); ret = target_write_u32(bank->target, EFM32_MSC_ADDRB, addr); if (ERROR_OK != ret) @@ -307,13 +307,13 @@ static int efm32x_erase_page(struct flash_bank *bank, uint32_t addr) if (ERROR_OK != ret) return ret; - LOG_DEBUG("status 0x%x", status); + LOG_DEBUG("status 0x%" PRIx32, status); if (status & EFM32_MSC_STATUS_LOCKED_MASK) { LOG_ERROR("Page is locked"); return ERROR_FAIL; } else if (status & EFM32_MSC_STATUS_INVADDR_MASK) { - LOG_ERROR("Invalid address 0x%x", addr); + LOG_ERROR("Invalid address 0x%" PRIx32, addr); return ERROR_FAIL; } @@ -681,13 +681,13 @@ static int efm32x_write_word(struct flash_bank *bank, uint32_t addr, if (ERROR_OK != ret) return ret; - LOG_DEBUG("status 0x%x", status); + LOG_DEBUG("status 0x%" PRIx32, status); if (status & EFM32_MSC_STATUS_LOCKED_MASK) { LOG_ERROR("Page is locked"); return ERROR_FAIL; } else if (status & EFM32_MSC_STATUS_INVADDR_MASK) { - LOG_ERROR("Invalid address 0x%x", addr); + LOG_ERROR("Invalid address 0x%" PRIx32, addr); return ERROR_FAIL; } @@ -747,7 +747,7 @@ static int efm32x_write(struct flash_bank *bank, uint8_t *buffer, "for padding buffer"); return ERROR_FAIL; } - LOG_INFO("odd number of bytes to write (%d), extending to %d " + LOG_INFO("odd number of bytes to write (%" PRIu32 "), extending to %" PRIu32 " " "and padding with 0xff", old_count, count); memset(buffer, 0xff, count); buffer = memcpy(new_buffer, buffer, old_count); diff --git a/src/flash/nor/fm3.c b/src/flash/nor/fm3.c index 86e4cb241..70114da61 100644 --- a/src/flash/nor/fm3.c +++ b/src/flash/nor/fm3.c @@ -195,7 +195,7 @@ static int fm3_busy_wait(struct target *target, uint32_t offset, int timeout_ms) } if (retval == ERROR_OK) - LOG_DEBUG("fm3_busy_wait(%x) needs about %d ms", offset, ms); + LOG_DEBUG("fm3_busy_wait(%" PRIx32 ") needs about %d ms", offset, ms); return retval; } @@ -557,7 +557,7 @@ static int fm3_write_block(struct flash_bank *bank, uint8_t *buffer, } if (buf_get_u32(reg_params[5].value, 0, 32) != ERROR_OK) { - LOG_ERROR("Fujitsu MB9[A/B]FXXX: Flash programming ERROR (Timeout) -> Reg R3: %x", + LOG_ERROR("Fujitsu MB9[A/B]FXXX: Flash programming ERROR (Timeout) -> Reg R3: %" PRIx32, buf_get_u32(reg_params[5].value, 0, 32)); retval = ERROR_FLASH_OPERATION_FAILED; break; diff --git a/src/flash/nor/kinetis.c b/src/flash/nor/kinetis.c index 51e7676fa..59750db0a 100644 --- a/src/flash/nor/kinetis.c +++ b/src/flash/nor/kinetis.c @@ -553,12 +553,12 @@ static int kinetis_write(struct flash_bank *bank, uint8_t *buffer, /* fallback to longword write */ fallback = 1; LOG_WARNING("Kinetis L Series supports Program Longword execution only."); - LOG_DEBUG("flash write into PFLASH @08%X", offset); + LOG_DEBUG("flash write into PFLASH @08%" PRIX32, offset); } else if (kinfo->flash_class == FC_FLEX_NVM) { uint8_t ftfx_fstat; - LOG_DEBUG("flash write into FlexNVM @%08X", offset); + LOG_DEBUG("flash write into FlexNVM @%08" PRIX32, offset); /* make flex ram available */ result = kinetis_ftfx_command(bank, FTFx_CMD_SETFLEXRAM, 0x00ff0000, 0, 0, 0, 0, 0, 0, 0, 0, &ftfx_fstat); @@ -579,7 +579,7 @@ static int kinetis_write(struct flash_bank *bank, uint8_t *buffer, LOG_WARNING("ram not ready, fallback to slow longword write (FCNFG: %02X)", buf[0]); } } else { - LOG_DEBUG("flash write into PFLASH @08%X", offset); + LOG_DEBUG("flash write into PFLASH @08%" PRIX32, offset); } @@ -632,8 +632,8 @@ static int kinetis_write(struct flash_bank *bank, uint8_t *buffer, (void) memcpy(residual_buffer, &buffer[i+4*wc], residual_bc); } - LOG_DEBUG("write section @ %08X with length %d bytes", - offset + i, wc*4); + LOG_DEBUG("write section @ %08" PRIX32 " with length %" PRIu32 " bytes", + offset + i, (uint32_t)wc*4); /* write data to flexram as whole-words */ result = target_write_memory(bank->target, FLEXRAM, 4, wc, @@ -678,7 +678,7 @@ static int kinetis_write(struct flash_bank *bank, uint8_t *buffer, "for padding buffer"); return ERROR_FAIL; } - LOG_INFO("odd number of bytes to write (%d), extending to %d " + LOG_INFO("odd number of bytes to write (%" PRIu32 "), extending to %" PRIu32 " " "and padding with 0xff", old_count, count); memset(buffer, 0xff, count); buffer = memcpy(new_buffer, buffer, old_count); @@ -698,7 +698,7 @@ static int kinetis_write(struct flash_bank *bank, uint8_t *buffer, for (i = 0; i < count; i += 4) { uint8_t ftfx_fstat; - LOG_DEBUG("write longword @ %08X", offset + i); + LOG_DEBUG("write longword @ %08" PRIX32, (uint32_t)(offset + i)); uint8_t padding[4] = {0xff, 0xff, 0xff, 0xff}; memcpy(padding, buffer + i, MIN(4, count-i)); @@ -753,7 +753,7 @@ static int kinetis_read_part_info(struct flash_bank *bank) return result; fcfg2_pflsh = (kinfo->sim_fcfg2 >> 23) & 0x01; - LOG_DEBUG("SDID: 0x%08X FCFG1: 0x%08X FCFG2: 0x%08X", kinfo->sim_sdid, + LOG_DEBUG("SDID: 0x%08" PRIX32 " FCFG1: 0x%08" PRIX32 " FCFG2: 0x%08" PRIX32, kinfo->sim_sdid, kinfo->sim_fcfg1, kinfo->sim_fcfg2); fcfg1_nvmsize = (uint8_t)((kinfo->sim_fcfg1 >> 28) & 0x0f); @@ -821,7 +821,7 @@ static int kinetis_read_part_info(struct flash_bank *bank) break; } - LOG_DEBUG("FlexNVM: %d PFlash: %d FlexRAM: %d PFLSH: %d", + LOG_DEBUG("FlexNVM: %" PRIu32 " PFlash: %" PRIu32 " FlexRAM: %" PRIu32 " PFLSH: %d", nvm_size, pf_size, ee_size, fcfg2_pflsh); if (kinfo->klxx) num_blocks = 1; diff --git a/src/flash/nor/lpc2000.c b/src/flash/nor/lpc2000.c index aadb9999a..c0c7e41ee 100644 --- a/src/flash/nor/lpc2000.c +++ b/src/flash/nor/lpc2000.c @@ -485,7 +485,7 @@ static int lpc2000_iap_call(struct flash_bank *bank, struct working_area *iap_wo result_table[3] = target_buffer_get_u32(target, mem_params[1].value + 0x10); LOG_DEBUG("IAP command = %i (0x%8.8" PRIx32 ", 0x%8.8" PRIx32 ", 0x%8.8" PRIx32 ", 0x%8.8" PRIx32 ", 0x%8.8" PRIx32 - ") completed with result = %8.8" PRIx32, + ") completed with result = %8.8x", code, param_table[0], param_table[1], param_table[2], param_table[3], param_table[4], status_code); destroy_mem_param(&mem_params[0]); diff --git a/src/flash/nor/lpcspifi.c b/src/flash/nor/lpcspifi.c index 0c12e6418..dc964b90a 100644 --- a/src/flash/nor/lpcspifi.c +++ b/src/flash/nor/lpcspifi.c @@ -199,7 +199,7 @@ static int lpcspifi_set_hw_mode(struct flash_bank *bank) return retval; } - LOG_DEBUG("Writing algorithm to working area at 0x%08x", + LOG_DEBUG("Writing algorithm to working area at 0x%08" PRIx32, spifi_init_algorithm->address); /* Write algorithm to working area */ retval = target_write_buffer(target, @@ -715,7 +715,7 @@ static int lpcspifi_write(struct flash_bank *bank, uint8_t *buffer, LOG_WARNING("Working area size is limited; flash writes may be"\ " slow. Increase working area size to at least %zdB"\ " to reduce write times.", - sizeof(lpcspifi_flash_write_code) + page_size + (size_t)(sizeof(lpcspifi_flash_write_code) + page_size) ); else if (fifo_size > 0x2000) /* Beyond this point, we start to get diminishing returns */ fifo_size = 0x2000; @@ -947,7 +947,7 @@ static int get_lpcspifi_info(struct flash_bank *bank, char *buf, int buf_size) } snprintf(buf, buf_size, "\nSPIFI flash information:\n" - " Device \'%s\' (ID 0x%08x)\n", + " Device \'%s\' (ID 0x%08" PRIx32 ")\n", lpcspifi_info->dev->name, lpcspifi_info->dev->device_id); return ERROR_OK; diff --git a/src/flash/nor/nuc1x.c b/src/flash/nor/nuc1x.c index a5a14c8b6..da88134da 100644 --- a/src/flash/nor/nuc1x.c +++ b/src/flash/nor/nuc1x.c @@ -410,7 +410,7 @@ static int nuc1x_write(struct flash_bank *bank, uint8_t *buffer, /* program command */ for (i = 0; i < count; i += 4) { - LOG_DEBUG("write longword @ %08X", offset + i); + LOG_DEBUG("write longword @ %08" PRIX32, (uint32_t)(offset + i)); uint8_t padding[4] = {0xff, 0xff, 0xff, 0xff}; memcpy(padding, buffer + i, MIN(4, count-i)); @@ -495,7 +495,7 @@ static int nuc1x_probe(struct flash_bank *bank) } if (!(NuMicroParts[i].partno == 0x00000000)) { LOG_INFO("DeviceID : 0x%08" PRIx32 "", device_id); - LOG_INFO("Detect %s%CN!", NuMicroParts[i].partname, ('A'+(device_id>>28))); + LOG_INFO("Detect %s%cN!", NuMicroParts[i].partname, (char)('A'+(device_id>>28))); } else { LOG_INFO("No NUC Device Detected..."); return ERROR_FAIL; @@ -552,7 +552,7 @@ static int get_nuc1x_info(struct flash_bank *bank, char *buf, int buf_size) } if (!(NuMicroParts[i].partno == 0x00000000)) { LOG_INFO("DeviceID : 0x%08" PRIx32 "", device_id); - LOG_INFO("Detect %s%CN!", NuMicroParts[i].partname, ('A'+(device_id>>28))); + LOG_INFO("Detect %s%cN!", NuMicroParts[i].partname, (char)('A'+(device_id>>28))); } else { LOG_INFO("No NUC Device Detected..."); return ERROR_FAIL; diff --git a/src/flash/nor/stm32f2x.c b/src/flash/nor/stm32f2x.c index a7aba2b3b..1dee6230c 100644 --- a/src/flash/nor/stm32f2x.c +++ b/src/flash/nor/stm32f2x.c @@ -258,7 +258,7 @@ static int stm32x_unlock_reg(struct target *target) return retval; if (ctrl & FLASH_LOCK) { - LOG_ERROR("flash not unlocked STM32_FLASH_CR: %x", ctrl); + LOG_ERROR("flash not unlocked STM32_FLASH_CR: %" PRIx32, ctrl); return ERROR_TARGET_FAILURE; } @@ -290,7 +290,7 @@ static int stm32x_unlock_option_reg(struct target *target) return retval; if (ctrl & OPT_LOCK) { - LOG_ERROR("options not unlocked STM32_FLASH_OPTCR: %x", ctrl); + LOG_ERROR("options not unlocked STM32_FLASH_OPTCR: %" PRIx32, ctrl); return ERROR_TARGET_FAILURE; } @@ -589,7 +589,7 @@ static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer, LOG_ERROR("flash memory write protected"); if (error != 0) { - LOG_ERROR("flash write failed = %08x", error); + LOG_ERROR("flash write failed = %08" PRIx32, error); /* Clear but report errors */ target_write_u32(target, STM32_FLASH_SR, error); retval = ERROR_FAIL; diff --git a/src/flash/nor/stm32lx.c b/src/flash/nor/stm32lx.c index 70414cdcd..d36e518e9 100644 --- a/src/flash/nor/stm32lx.c +++ b/src/flash/nor/stm32lx.c @@ -598,14 +598,15 @@ static int stm32lx_probe(struct flash_bank *bank) /* This is the first bank */ flash_size_in_kb = first_bank_size_in_kb; } else { - LOG_WARNING("STM32L flash bank base address config is incorrect. 0x%x but should rather be 0x%x or 0x%x", + LOG_WARNING("STM32L flash bank base address config is incorrect." + " 0x%" PRIx32 " but should rather be 0x%" PRIx32 " or 0x%" PRIx32, bank->base, base_address, second_bank_base); return ERROR_FAIL; } - LOG_INFO("STM32L flash has dual banks. Bank (%d) size is %dkb, base address is 0x%x", + LOG_INFO("STM32L flash has dual banks. Bank (%d) size is %dkb, base address is 0x%" PRIx32, bank->bank_number, flash_size_in_kb, base_address); } else { - LOG_INFO("STM32L flash size is %dkb, base address is 0x%x", flash_size_in_kb, base_address); + LOG_INFO("STM32L flash size is %dkb, base address is 0x%" PRIx32, flash_size_in_kb, base_address); } /* if the user sets the size manually then ignore the probed value diff --git a/src/flash/nor/stmsmi.c b/src/flash/nor/stmsmi.c index 3c186fdd0..9a715ef94 100644 --- a/src/flash/nor/stmsmi.c +++ b/src/flash/nor/stmsmi.c @@ -638,7 +638,7 @@ static int get_stmsmi_info(struct flash_bank *bank, char *buf, int buf_size) } snprintf(buf, buf_size, "\nSMI flash information:\n" - " Device \'%s\' (ID 0x%08x)\n", + " Device \'%s\' (ID 0x%08" PRIx32 ")\n", stmsmi_info->dev->name, stmsmi_info->dev->device_id); return ERROR_OK; diff --git a/src/flash/nor/tcl.c b/src/flash/nor/tcl.c index 5bc0958be..916ebf738 100644 --- a/src/flash/nor/tcl.c +++ b/src/flash/nor/tcl.c @@ -74,7 +74,7 @@ COMMAND_HANDLER(handle_flash_info_command) return retval; command_print(CMD_CTX, - "#%" PRIu32 " : %s at 0x%8.8" PRIx32 ", size 0x%8.8" PRIx32 + "#%d : %s at 0x%8.8" PRIx32 ", size 0x%8.8" PRIx32 ", buswidth %i, chipwidth %i", p->bank_number, p->driver->name, @@ -236,7 +236,7 @@ COMMAND_HANDLER(handle_flash_erase_address_command) retval = flash_erase_address_range(target, do_pad, address, length); if ((ERROR_OK == retval) && (duration_measure(&bench) == ERROR_OK)) { - command_print(CMD_CTX, "erased address 0x%8.8x (length %i)" + command_print(CMD_CTX, "erased address 0x%8.8" PRIx32 " (length %" PRIi32 ")" " in %fs (%0.3f KiB/s)", address, length, duration_elapsed(&bench), duration_kbps(&bench, length)); } @@ -294,7 +294,7 @@ COMMAND_HANDLER(handle_flash_erase_command) if ((ERROR_OK == retval) && (duration_measure(&bench) == ERROR_OK)) { command_print(CMD_CTX, "erased sectors %" PRIu32 " " - "through %" PRIu32 " on flash bank %" PRIu32 " " + "through %" PRIu32 " on flash bank %d " "in %fs", first, last, p->bank_number, duration_elapsed(&bench)); } @@ -332,7 +332,7 @@ COMMAND_HANDLER(handle_flash_protect_command) retval = flash_driver_protect(p, set, first, last); if (retval == ERROR_OK) { command_print(CMD_CTX, "%s protection for sectors %i " - "through %i on flash bank %" PRIu32 "", + "through %i on flash bank %d", (set) ? "set" : "cleared", (int) first, (int) last, p->bank_number); } @@ -818,7 +818,7 @@ COMMAND_HANDLER(handle_flash_banks_command) unsigned n = 0; for (struct flash_bank *p = flash_bank_list(); p; p = p->next, n++) { - LOG_USER("#%" PRIu32 " : %s (%s) at 0x%8.8" PRIx32 ", size 0x%8.8" PRIx32 ", " + LOG_USER("#%d : %s (%s) at 0x%8.8" PRIx32 ", size 0x%8.8" PRIx32 ", " "buswidth %u, chipwidth %u", p->bank_number, p->name, p->driver->name, p->base, p->size, p->bus_width, p->chip_width); diff --git a/src/target/adi_v5_swd.c b/src/target/adi_v5_swd.c index 01782e5f4..027e06696 100644 --- a/src/target/adi_v5_swd.c +++ b/src/target/adi_v5_swd.c @@ -209,7 +209,7 @@ COMMAND_HANDLER(handle_swd_wcr) } command_print(CMD_CTX, - "turnaround=%d, prescale=%d", + "turnaround=%" PRIu32 ", prescale=%" PRIu32, WCR_TO_TRN(wcr), WCR_TO_PRESCALE(wcr)); return ERROR_OK; @@ -330,7 +330,7 @@ static int swd_init(struct command_context *ctx) status = swd_queue_idcode_read(dap, &ack, &idcode); if (status == ERROR_OK) - LOG_INFO("SWD IDCODE %#8.8x", idcode); + LOG_INFO("SWD IDCODE %#8.8" PRIx32, idcode); return status; diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c index 7687466f8..6b1a1731b 100644 --- a/src/target/arm7_9_common.c +++ b/src/target/arm7_9_common.c @@ -103,7 +103,7 @@ static void arm7_9_assign_wp(struct arm7_9_common *arm7_9, struct breakpoint *br arm7_9->wp_available--; } else LOG_ERROR("BUG: no hardware comparator available"); - LOG_DEBUG("BPID: %d (0x%08" PRIx32 ") using hw wp: %d", + LOG_DEBUG("BPID: %" PRId32 " (0x%08" PRIx32 ") using hw wp: %d", breakpoint->unique_id, breakpoint->address, breakpoint->set); @@ -189,7 +189,7 @@ static int arm7_9_set_breakpoint(struct target *target, struct breakpoint *break struct arm7_9_common *arm7_9 = target_to_arm7_9(target); int retval = ERROR_OK; - LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32 ", Type: %d", + LOG_DEBUG("BPID: %" PRId32 ", Address: 0x%08" PRIx32 ", Type: %d", breakpoint->unique_id, breakpoint->address, breakpoint->type); @@ -301,7 +301,7 @@ static int arm7_9_unset_breakpoint(struct target *target, struct breakpoint *bre int retval = ERROR_OK; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32, + LOG_DEBUG("BPID: %" PRId32 ", Address: 0x%08" PRIx32, breakpoint->unique_id, breakpoint->address); @@ -311,7 +311,7 @@ static int arm7_9_unset_breakpoint(struct target *target, struct breakpoint *bre } if (breakpoint->type == BKPT_HARD) { - LOG_DEBUG("BPID: %d Releasing hw wp: %d", + LOG_DEBUG("BPID: %" PRId32 " Releasing hw wp: %d", breakpoint->unique_id, breakpoint->set); if (breakpoint->set == 1) { @@ -1719,7 +1719,7 @@ int arm7_9_resume(struct target *target, breakpoint = breakpoint_find(target, buf_get_u32(arm->pc->value, 0, 32)); if (breakpoint != NULL) { - LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (id: %d)", + LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (id: %" PRId32, breakpoint->address, breakpoint->unique_id); retval = arm7_9_unset_breakpoint(target, breakpoint); diff --git a/src/target/arm946e.c b/src/target/arm946e.c index 5c85845d1..fb50d694c 100644 --- a/src/target/arm946e.c +++ b/src/target/arm946e.c @@ -596,7 +596,7 @@ static int jim_arm946e_cp15(Jim_Interp *interp, int argc, Jim_Obj * const *argv) if (retval != ERROR_OK) return JIM_ERR; char buf[20]; - sprintf(buf, "0x%08x", value); + sprintf(buf, "0x%08" PRIx32, value); /* Return value in hex format */ Jim_SetResultString(interp, buf, -1); } else if (argc == 3) { @@ -643,7 +643,8 @@ COMMAND_HANDLER(arm946e_handle_idcache) if (csize == 0) command_print(CMD_CTX, "%s-cache absent", icache ? "I" : "D"); else - command_print(CMD_CTX, "%s-cache size: %dK, %s", icache ? "I" : "D", csize, bena ? "enabled" : "disabled"); + command_print(CMD_CTX, "%s-cache size: %" PRIu32 "K, %s", + icache ? "I" : "D", csize, bena ? "enabled" : "disabled"); return ERROR_OK; } diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c index 68af7f34d..ba8e38015 100644 --- a/src/target/arm_adi_v5.c +++ b/src/target/arm_adi_v5.c @@ -662,7 +662,7 @@ int dap_syssec_kinetis_mdmap(struct adiv5_dap *dap) dap_run(dap); if (val != 0x001C0000) { - LOG_DEBUG("id doesn't match %08X != 0x001C0000", val); + LOG_DEBUG("id doesn't match %08" PRIX32 " != 0x001C0000", val); dap_ap_select(dap, 0); return ERROR_FAIL; } @@ -676,7 +676,7 @@ int dap_syssec_kinetis_mdmap(struct adiv5_dap *dap) return retval; dap_run(dap); - LOG_DEBUG("MDM_REG_STAT %08X", val); + LOG_DEBUG("MDM_REG_STAT %08" PRIX32, val); if ((val & (MDM_STAT_SYSSEC|MDM_STAT_FREADY)) != (MDM_STAT_FREADY)) { LOG_DEBUG("MDMAP: system is secured, masserase needed"); @@ -704,7 +704,7 @@ int dap_syssec_kinetis_mdmap(struct adiv5_dap *dap) if (retval != ERROR_OK) return retval; dap_run(dap); - LOG_DEBUG("MDM_REG_STAT %08X", val); + LOG_DEBUG("MDM_REG_STAT %08" PRIX32, val); if ((val & 1)) break; @@ -720,13 +720,13 @@ int dap_syssec_kinetis_mdmap(struct adiv5_dap *dap) if (retval != ERROR_OK) return retval; dap_run(dap); - LOG_DEBUG("MDM_REG_STAT %08X", val); + LOG_DEBUG("MDM_REG_STAT %08" PRIX32, val); /* read control register and wait for ready */ retval = dap_queue_ap_read(dap, MDM_REG_CTRL, &val); if (retval != ERROR_OK) return retval; dap_run(dap); - LOG_DEBUG("MDM_REG_CTRL %08X", val); + LOG_DEBUG("MDM_REG_CTRL %08" PRIX32, val); if (val == 0x00) break; @@ -765,7 +765,7 @@ int dap_syssec(struct adiv5_dap *dap) while (tap != NULL) { if (tap->hasidcode && (dap_syssec_filter_data[i].idcode == tap->idcode)) { - LOG_DEBUG("DAP: mdmap_init for idcode: %08x", tap->idcode); + LOG_DEBUG("DAP: mdmap_init for idcode: %08" PRIx32, tap->idcode); dap_syssec_filter_data[i].dap_init(dap); } tap = tap->next_tap; @@ -963,7 +963,7 @@ int dap_find_ap(struct adiv5_dap *dap, enum ap_type type_to_find, uint8_t *ap_nu ((id_val & 0x0FFF0000) == 0x04770000) && /* Jedec codes match */ ((id_val & 0xFF) == type_to_find)) { /* type matches*/ - LOG_DEBUG("Found %s at AP index: %d (IDR=0x%08X)", + LOG_DEBUG("Found %s at AP index: %d (IDR=0x%08" PRIX32 ")", (type_to_find == AP_TYPE_AHB_AP) ? "AHB-AP" : (type_to_find == AP_TYPE_APB_AP) ? "APB-AP" : (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown", diff --git a/src/target/arm_adi_v5.h b/src/target/arm_adi_v5.h index f2f29a47b..f5c185c92 100644 --- a/src/target/arm_adi_v5.h +++ b/src/target/arm_adi_v5.h @@ -60,8 +60,8 @@ #define DP_SELECT 0x8 /* JTAG: r/w; SWD: write */ #define DP_RDBUFF 0xC /* read-only */ -#define WCR_TO_TRN(wcr) (1 + (3 & ((wcr)) >> 8)) /* 1..4 clocks */ -#define WCR_TO_PRESCALE(wcr) (7 & ((wcr))) /* impl defined */ +#define WCR_TO_TRN(wcr) ((uint32_t)(1 + (3 & ((wcr)) >> 8))) /* 1..4 clocks */ +#define WCR_TO_PRESCALE(wcr) ((uint32_t)(7 & ((wcr)))) /* impl defined */ /* Fields of the DP's AP ABORT register */ #define DAPABORT (1 << 0) diff --git a/src/target/armv7a.c b/src/target/armv7a.c index 80d7a6e8b..6a41e0dbd 100644 --- a/src/target/armv7a.c +++ b/src/target/armv7a.c @@ -110,8 +110,8 @@ static int armv7a_read_ttbcr(struct target *target) armv7a->armv7a_mmu.ttbr0_mask); #endif if (armv7a->armv7a_mmu.ttbr1_used == 1) { - LOG_INFO("SVC access above %x", - (0xffffffff & armv7a->armv7a_mmu.ttbr0_mask)); + LOG_INFO("SVC access above %" PRIx32, + (uint32_t)(0xffffffff & armv7a->armv7a_mmu.ttbr0_mask)); armv7a->armv7a_mmu.os_border = 0xffffffff & armv7a->armv7a_mmu.ttbr0_mask; } else { /* fix me , default is hard coded LINUX border */ @@ -257,7 +257,7 @@ int armv7a_mmu_translate_va_pa(struct target *target, uint32_t va, if (*val == va) LOG_WARNING("virt = phys : MMU disable !!"); if (meminfo) { - LOG_INFO("%x : %x %s outer shareable %s secured", + LOG_INFO("%" PRIx32 " : %" PRIx32 " %s outer shareable %s secured", va, *val, NOS == 1 ? "not" : " ", NS == 1 ? "not" : ""); @@ -295,7 +295,7 @@ int armv7a_mmu_translate_va_pa(struct target *target, uint32_t va, LOG_INFO("inner: Write-Back, no Write-Allocate"); default: - LOG_INFO("inner: %x ???", INNER); + LOG_INFO("inner: %" PRIx32 " ???", INNER); } } @@ -314,14 +314,14 @@ static int armv7a_handle_inner_cache_info_command(struct command_context *cmd_ct } command_print(cmd_ctx, - "D-Cache: linelen %i, associativity %i, nsets %i, cachesize %d KBytes", + "D-Cache: linelen %" PRIi32 ", associativity %" PRIi32 ", nsets %" PRIi32 ", cachesize %" PRId32 " KBytes", armv7a_cache->d_u_size.linelen, armv7a_cache->d_u_size.associativity, armv7a_cache->d_u_size.nsets, armv7a_cache->d_u_size.cachesize); command_print(cmd_ctx, - "I-Cache: linelen %i, associativity %i, nsets %i, cachesize %d KBytes", + "I-Cache: linelen %" PRIi32 ", associativity %" PRIi32 ", nsets %" PRIi32 ", cachesize %" PRId32 " KBytes", armv7a_cache->i_size.linelen, armv7a_cache->i_size.associativity, armv7a_cache->i_size.nsets, @@ -388,7 +388,7 @@ static int armv7a_flush_all_data(struct target *target) while (head != (struct target_list *)NULL) { curr = head->target; if (curr->state == TARGET_HALTED) { - LOG_INFO("Wait flushing data l1 on core %d", curr->coreid); + LOG_INFO("Wait flushing data l1 on core %" PRId32, curr->coreid); retval = _armv7a_flush_all_data(curr); } head = head->next; @@ -434,19 +434,19 @@ static int armv7a_handle_l2x_cache_info_command(struct command_context *cmd_ctx, } command_print(cmd_ctx, - "L1 D-Cache: linelen %i, associativity %i, nsets %i, cachesize %d KBytes", + "L1 D-Cache: linelen %" PRIi32 ", associativity %" PRIi32 ", nsets %" PRIi32 ", cachesize %" PRId32 " KBytes", armv7a_cache->d_u_size.linelen, armv7a_cache->d_u_size.associativity, armv7a_cache->d_u_size.nsets, armv7a_cache->d_u_size.cachesize); command_print(cmd_ctx, - "L1 I-Cache: linelen %i, associativity %i, nsets %i, cachesize %d KBytes", + "L1 I-Cache: linelen %" PRIi32 ", associativity %" PRIi32 ", nsets %" PRIi32 ", cachesize %" PRId32 " KBytes", armv7a_cache->i_size.linelen, armv7a_cache->i_size.associativity, armv7a_cache->i_size.nsets, armv7a_cache->i_size.cachesize); - command_print(cmd_ctx, "L2 unified cache Base Address 0x%x, %d ways", + command_print(cmd_ctx, "L2 unified cache Base Address 0x%" PRIx32 ", %" PRId32 " ways", l2x_cache->base, l2x_cache->way); @@ -587,7 +587,7 @@ int armv7a_identify_cache(struct target *target) if (retval != ERROR_OK) goto done; clidr = (clidr & 0x7000000) >> 23; - LOG_INFO("number of cache level %d", clidr / 2); + LOG_INFO("number of cache level %" PRIx32, (uint32_t)(clidr / 2)); if ((clidr / 2) > 1) { /* FIXME not supported present in cortex A8 and later */ /* in cortex A7, A15 */ diff --git a/src/target/avr32_ap7k.c b/src/target/avr32_ap7k.c index 12bea6675..70af8c3ed 100644 --- a/src/target/avr32_ap7k.c +++ b/src/target/avr32_ap7k.c @@ -544,7 +544,7 @@ static int avr32_ap7k_examine(struct target *target) if (!target_was_examined(target)) { target_set_examined(target); avr32_jtag_nexus_read(&ap7k->jtag, AVR32_OCDREG_DID, &devid); - LOG_INFO("device id: %08x", devid); + LOG_INFO("device id: %08" PRIx32, devid); avr32_ocd_setbits(&ap7k->jtag, AVR32_OCDREG_DC, OCDREG_DC_DBE); avr32_jtag_nexus_read(&ap7k->jtag, AVR32_OCDREG_DS, &ds); diff --git a/src/target/breakpoints.c b/src/target/breakpoints.c index 422705bc9..5143afb7b 100644 --- a/src/target/breakpoints.c +++ b/src/target/breakpoints.c @@ -62,7 +62,7 @@ int breakpoint_add_internal(struct target *target, * breakpoint" ... check all the parameters before * succeeding. */ - LOG_DEBUG("Duplicate Breakpoint address: 0x%08" PRIx32 " (BP %d)", + LOG_DEBUG("Duplicate Breakpoint address: 0x%08" PRIx32 " (BP %" PRIu32 ")", address, breakpoint->unique_id); return ERROR_OK; } @@ -100,7 +100,7 @@ fail: return retval; } - LOG_DEBUG("added %s breakpoint at 0x%8.8" PRIx32 " of length 0x%8.8x, (BPID: %d)", + LOG_DEBUG("added %s breakpoint at 0x%8.8" PRIx32 " of length 0x%8.8x, (BPID: %" PRIu32 ")", breakpoint_type_strings[(*breakpoint_p)->type], (*breakpoint_p)->address, (*breakpoint_p)->length, (*breakpoint_p)->unique_id); @@ -126,7 +126,7 @@ int context_breakpoint_add_internal(struct target *target, * breakpoint" ... check all the parameters before * succeeding. */ - LOG_DEBUG("Duplicate Breakpoint asid: 0x%08" PRIx32 " (BP %d)", + LOG_DEBUG("Duplicate Breakpoint asid: 0x%08" PRIx32 " (BP %" PRIu32 ")", asid, breakpoint->unique_id); return -1; } @@ -152,7 +152,7 @@ int context_breakpoint_add_internal(struct target *target, return retval; } - LOG_DEBUG("added %s Context breakpoint at 0x%8.8" PRIx32 " of length 0x%8.8x, (BPID: %d)", + LOG_DEBUG("added %s Context breakpoint at 0x%8.8" PRIx32 " of length 0x%8.8x, (BPID: %" PRIu32 ")", breakpoint_type_strings[(*breakpoint_p)->type], (*breakpoint_p)->asid, (*breakpoint_p)->length, (*breakpoint_p)->unique_id); @@ -178,11 +178,11 @@ int hybrid_breakpoint_add_internal(struct target *target, * breakpoint" ... check all the parameters before * succeeding. */ - LOG_DEBUG("Duplicate Hybrid Breakpoint asid: 0x%08" PRIx32 " (BP %d)", + LOG_DEBUG("Duplicate Hybrid Breakpoint asid: 0x%08" PRIx32 " (BP %" PRIu32 ")", asid, breakpoint->unique_id); return -1; } else if ((breakpoint->address == address) && (breakpoint->asid == 0)) { - LOG_DEBUG("Duplicate Breakpoint IVA: 0x%08" PRIx32 " (BP %d)", + LOG_DEBUG("Duplicate Breakpoint IVA: 0x%08" PRIx32 " (BP %" PRIu32 ")", address, breakpoint->unique_id); return -1; @@ -210,7 +210,7 @@ int hybrid_breakpoint_add_internal(struct target *target, return retval; } LOG_DEBUG( - "added %s Hybrid breakpoint at address 0x%8.8" PRIx32 " of length 0x%8.8x, (BPID: %d)", + "added %s Hybrid breakpoint at address 0x%8.8" PRIx32 " of length 0x%8.8x, (BPID: %" PRIu32 ")", breakpoint_type_strings[(*breakpoint_p)->type], (*breakpoint_p)->address, (*breakpoint_p)->length, @@ -306,7 +306,7 @@ static void breakpoint_free(struct target *target, struct breakpoint *breakpoint retval = target_remove_breakpoint(target, breakpoint); - LOG_DEBUG("free BPID: %d --> %d", breakpoint->unique_id, retval); + LOG_DEBUG("free BPID: %" PRIu32 " --> %d", breakpoint->unique_id, retval); (*breakpoint_p) = breakpoint->next; free(breakpoint->orig_instr); free(breakpoint); diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c index 4649f6c7d..85f22474a 100644 --- a/src/target/cortex_a.c +++ b/src/target/cortex_a.c @@ -102,14 +102,14 @@ static int cortex_a8_check_address(struct target *target, uint32_t address) uint32_t os_border = armv7a->armv7a_mmu.os_border; if ((address < os_border) && (armv7a->arm.core_mode == ARM_MODE_SVC)) { - LOG_ERROR("%x access in userspace and target in supervisor", address); + LOG_ERROR("%" PRIx32 " access in userspace and target in supervisor", address); return ERROR_FAIL; } if ((address >= os_border) && (cortex_a8->curr_mode != ARM_MODE_SVC)) { dpm_modeswitch(&armv7a->dpm, ARM_MODE_SVC); cortex_a8->curr_mode = ARM_MODE_SVC; - LOG_INFO("%x access in kernel space and target not in supervisor", + LOG_INFO("%" PRIx32 " access in kernel space and target not in supervisor", address); return ERROR_OK; } @@ -1911,7 +1911,7 @@ static int cortex_a8_write_apb_ab_memory(struct target *target, goto error_free_buff_w; if (dscr & (DSCR_STICKY_ABORT_PRECISE | DSCR_STICKY_ABORT_IMPRECISE)) { /* Abort occurred - clear it and exit */ - LOG_ERROR("abort occurred - dscr = 0x%08x", dscr); + LOG_ERROR("abort occurred - dscr = 0x%08" PRIx32, dscr); mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap, armv7a->debug_base + CPUDBG_DRCR, 1<<2); goto error_free_buff_w; @@ -2054,7 +2054,7 @@ static int cortex_a8_read_apb_ab_memory(struct target *target, goto error_free_buff_r; if (dscr & (DSCR_STICKY_ABORT_PRECISE | DSCR_STICKY_ABORT_IMPRECISE)) { /* Abort occurred - clear it and exit */ - LOG_ERROR("abort occurred - dscr = 0x%08x", dscr); + LOG_ERROR("abort occurred - dscr = 0x%08" PRIx32, dscr); mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap, armv7a->debug_base + CPUDBG_DRCR, 1<<2); goto error_free_buff_r; @@ -2104,7 +2104,7 @@ static int cortex_a8_read_phys_memory(struct target *target, struct adiv5_dap *swjdp = armv7a->arm.dap; int retval = ERROR_COMMAND_SYNTAX_ERROR; uint8_t apsel = swjdp->apsel; - LOG_DEBUG("Reading memory at real address 0x%x; size %d; count %d", + LOG_DEBUG("Reading memory at real address 0x%" PRIx32 "; size %" PRId32 "; count %" PRId32, address, size, count); if (count && buffer) { @@ -2153,7 +2153,7 @@ static int cortex_a8_read_memory(struct target *target, uint32_t address, uint8_t apsel = swjdp->apsel; /* cortex_a8 handles unaligned memory access */ - LOG_DEBUG("Reading memory at address 0x%x; size %d; count %d", address, + LOG_DEBUG("Reading memory at address 0x%" PRIx32 "; size %" PRId32 "; count %" PRId32, address, size, count); if (armv7a->memory_ap_available && (apsel == armv7a->memory_ap)) { if (!armv7a->is_armv7r) { @@ -2168,7 +2168,7 @@ static int cortex_a8_read_memory(struct target *target, uint32_t address, if (retval != ERROR_OK) return retval; - LOG_DEBUG("Reading at virtual address. Translating v:0x%x to r:0x%x", + LOG_DEBUG("Reading at virtual address. Translating v:0x%" PRIx32 " to r:0x%" PRIx32, virt, phys); address = phys; } @@ -2198,7 +2198,7 @@ static int cortex_a8_write_phys_memory(struct target *target, int retval = ERROR_COMMAND_SYNTAX_ERROR; uint8_t apsel = swjdp->apsel; - LOG_DEBUG("Writing memory to real address 0x%x; size %d; count %d", address, + LOG_DEBUG("Writing memory to real address 0x%" PRIx32 "; size %" PRId32 "; count %" PRId32, address, size, count); if (count && buffer) { @@ -2302,11 +2302,11 @@ static int cortex_a8_write_memory(struct target *target, uint32_t address, struct adiv5_dap *swjdp = armv7a->arm.dap; uint8_t apsel = swjdp->apsel; /* cortex_a8 handles unaligned memory access */ - LOG_DEBUG("Writing memory at address 0x%x; size %d; count %d", address, + LOG_DEBUG("Writing memory at address 0x%" PRIx32 "; size %" PRId32 "; count %" PRId32, address, size, count); if (armv7a->memory_ap_available && (apsel == armv7a->memory_ap)) { - LOG_DEBUG("Writing memory to address 0x%x; size %d; count %d", address, size, + LOG_DEBUG("Writing memory to address 0x%" PRIx32 "; size %" PRId32 "; count %" PRId32, address, size, count); if (!armv7a->is_armv7r) { retval = cortex_a8_mmu(target, &enabled); @@ -2318,7 +2318,7 @@ static int cortex_a8_write_memory(struct target *target, uint32_t address, retval = cortex_a8_virt2phys(target, virt, &phys); if (retval != ERROR_OK) return retval; - LOG_DEBUG("Writing to virtual address. Translating v:0x%x to r:0x%x", + LOG_DEBUG("Writing to virtual address. Translating v:0x%" PRIx32 " to r:0x%" PRIx32, virt, phys); address = phys; @@ -2696,7 +2696,7 @@ COMMAND_HANDLER(cortex_a8_handle_smp_gdb_command) target->gdb_service->core[1] = coreid; } - command_print(CMD_CTX, "gdb coreid %d -> %d", target->gdb_service->core[0] + command_print(CMD_CTX, "gdb coreid %" PRId32 " -> %" PRId32, target->gdb_service->core[0] , target->gdb_service->core[1]); } return ERROR_OK; diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c index 44763943f..578f6eebb 100644 --- a/src/target/cortex_m.c +++ b/src/target/cortex_m.c @@ -771,7 +771,7 @@ static int cortex_m_resume(struct target *target, int current, /* Single step past breakpoint at current address */ breakpoint = breakpoint_find(target, resume_pc); if (breakpoint) { - LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (ID: %d)", + LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (ID: %" PRIu32 ")", breakpoint->address, breakpoint->unique_id); cortex_m_unset_breakpoint(target, breakpoint); @@ -1129,7 +1129,7 @@ int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint struct cortex_m_fp_comparator *comparator_list = cortex_m->fp_comparator_list; if (breakpoint->set) { - LOG_WARNING("breakpoint (BPID: %d) already set", breakpoint->unique_id); + LOG_WARNING("breakpoint (BPID: %" PRIu32 ") already set", breakpoint->unique_id); return ERROR_OK; } @@ -1185,7 +1185,7 @@ int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint breakpoint->set = true; } - LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)", + LOG_DEBUG("BPID: %" PRIu32 ", Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)", breakpoint->unique_id, (int)(breakpoint->type), breakpoint->address, @@ -1206,7 +1206,7 @@ int cortex_m_unset_breakpoint(struct target *target, struct breakpoint *breakpoi return ERROR_OK; } - LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)", + LOG_DEBUG("BPID: %" PRIu32 ", Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)", breakpoint->unique_id, (int)(breakpoint->type), breakpoint->address, diff --git a/src/target/dsp563xx.c b/src/target/dsp563xx.c index 97348e45f..07df36338 100644 --- a/src/target/dsp563xx.c +++ b/src/target/dsp563xx.c @@ -580,7 +580,7 @@ static int dsp563xx_reg_pc_read(struct target *target) /* conditional branch check */ if (once_regs[ONCE_REG_IDX_OPABDR].reg == once_regs[ONCE_REG_IDX_OPABEX].reg) { if ((once_regs[ONCE_REG_IDX_OPABF11].reg & 1) == 0) { - LOG_DEBUG("%s conditional branch not supported yet (0x%x 0x%x 0x%x)", + LOG_DEBUG("%s conditional branch not supported yet (0x%" PRIx32 " 0x%" PRIx32 " 0x%" PRIx32 ")", __func__, (once_regs[ONCE_REG_IDX_OPABF11].reg >> 1), once_regs[ONCE_REG_IDX_OPABDR].reg, @@ -938,7 +938,7 @@ static int dsp563xx_examine(struct target *target) if (((chip>>5)&0x1f) == 0) chip += 300; - LOG_INFO("DSP56%03d device found", chip); + LOG_INFO("DSP56%03" PRId32 " device found", chip); /* Clear all breakpoints */ dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OBCR, 0); @@ -1079,8 +1079,8 @@ static int dsp563xx_poll(struct target *target) else target_call_event_callbacks(target, TARGET_EVENT_HALTED); - LOG_DEBUG("target->state: %s (%x)", target_state_name(target), once_status); - LOG_INFO("halted: PC: 0x%x", dsp563xx->core_regs[DSP563XX_REG_IDX_PC]); + LOG_DEBUG("target->state: %s (%" PRIx32 ")", target_state_name(target), once_status); + LOG_INFO("halted: PC: 0x%" PRIx32, dsp563xx->core_regs[DSP563XX_REG_IDX_PC]); } } @@ -1310,7 +1310,7 @@ static int dsp563xx_step(struct target *target, target->debug_reason = DBG_REASON_SINGLESTEP; target_call_event_callbacks(target, TARGET_EVENT_HALTED); - LOG_INFO("halted: PC: 0x%x", dsp563xx->core_regs[DSP563XX_REG_IDX_PC]); + LOG_INFO("halted: PC: 0x%" PRIx32, dsp563xx->core_regs[DSP563XX_REG_IDX_PC]); return err; } @@ -1965,7 +1965,7 @@ static int dsp563xx_add_custom_watchpoint(struct target *target, uint32_t addres obcr_value |= OBCR_BP_MEM_P; break; default: - LOG_ERROR("Unknown memType parameter (%d)", memType); + LOG_ERROR("Unknown memType parameter (%" PRIu32 ")", memType); err = ERROR_TARGET_INVALID; } } diff --git a/src/target/dsp5680xx.c b/src/target/dsp5680xx.c index 1563b6458..f72d33637 100644 --- a/src/target/dsp5680xx.c +++ b/src/target/dsp5680xx.c @@ -1125,7 +1125,7 @@ static int dsp5680xx_read_16_single(struct target *t, uint32_t a, /* at this point the data i want is at the reg eonce can read */ retval = core_rx_lower_data(target, data_read); err_check_propagate(retval); - LOG_DEBUG("%s:Data read from 0x%06X: 0x%02X%02X", __func__, address, + LOG_DEBUG("%s:Data read from 0x%06" PRIX32 ": 0x%02X%02X", __func__, address, data_read[1], data_read[0]); return retval; } @@ -1170,8 +1170,8 @@ static int dsp5680xx_read_32_single(struct target *t, uint32_t a, return retval; } -static int dsp5680xx_read(struct target *t, uint32_t a, unsigned size, - unsigned count, uint8_t *buf) +static int dsp5680xx_read(struct target *t, uint32_t a, uint32_t size, + uint32_t count, uint8_t *buf) { struct target *target = t; @@ -1307,7 +1307,7 @@ static int dsp5680xx_write_8(struct target *t, uint32_t a, uint32_t c, dsp5680xx_write_16_single(target, address + iter, data_16, pmem); if (retval != ERROR_OK) { - LOG_ERROR("%s: Could not write to p:0x%04X", __func__, + LOG_ERROR("%s: Could not write to p:0x%04" PRIX32, __func__, address); dsp5680xx_context.flush = 1; return retval; @@ -1364,7 +1364,7 @@ static int dsp5680xx_write_16(struct target *t, uint32_t a, uint32_t c, dsp5680xx_write_16_single(target, address + iter, data[iter], pmem); if (retval != ERROR_OK) { - LOG_ERROR("%s: Could not write to p:0x%04X", __func__, + LOG_ERROR("%s: Could not write to p:0x%04" PRIX32, __func__, address); dsp5680xx_context.flush = 1; return retval; @@ -1401,7 +1401,7 @@ static int dsp5680xx_write_32(struct target *t, uint32_t a, uint32_t c, dsp5680xx_write_32_single(target, address + (iter << 1), data[iter], pmem); if (retval != ERROR_OK) { - LOG_ERROR("%s: Could not write to p:0x%04X", __func__, + LOG_ERROR("%s: Could not write to p:0x%04" PRIX32, __func__, address); dsp5680xx_context.flush = 1; return retval; diff --git a/src/target/hla_target.c b/src/target/hla_target.c index abbc1b194..903409441 100644 --- a/src/target/hla_target.c +++ b/src/target/hla_target.c @@ -483,7 +483,7 @@ static int adapter_poll(struct target *target) target_call_event_callbacks(target, TARGET_EVENT_HALTED); } - LOG_DEBUG("halted: PC: 0x%08x", buf_get_u32(armv7m->arm.pc->value, 0, 32)); + LOG_DEBUG("halted: PC: 0x%08" PRIx32, buf_get_u32(armv7m->arm.pc->value, 0, 32)); } return ERROR_OK; @@ -610,7 +610,7 @@ static int adapter_resume(struct target *target, int current, struct breakpoint *breakpoint = NULL; struct reg *pc; - LOG_DEBUG("%s %d 0x%08x %d %d", __func__, current, address, + LOG_DEBUG("%s %d 0x%08" PRIx32 " %d %d", __func__, current, address, handle_breakpoints, debug_execution); if (target->state != TARGET_HALTED) { @@ -658,7 +658,7 @@ static int adapter_resume(struct target *target, int current, /* Single step past breakpoint at current address */ breakpoint = breakpoint_find(target, resume_pc); if (breakpoint) { - LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (ID: %d)", + LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (ID: %" PRIu32 ")", breakpoint->address, breakpoint->unique_id); cortex_m_unset_breakpoint(target, breakpoint); @@ -749,7 +749,7 @@ static int adapter_step(struct target *target, int current, adapter_debug_entry(target); target_call_event_callbacks(target, TARGET_EVENT_HALTED); - LOG_INFO("halted: PC: 0x%08x", buf_get_u32(armv7m->arm.pc->value, 0, 32)); + LOG_INFO("halted: PC: 0x%08" PRIx32, buf_get_u32(armv7m->arm.pc->value, 0, 32)); return ERROR_OK; } @@ -763,7 +763,7 @@ static int adapter_read_memory(struct target *target, uint32_t address, if (!count || !buffer) return ERROR_COMMAND_SYNTAX_ERROR; - LOG_DEBUG("%s 0x%08x %d %d", __func__, address, size, count); + LOG_DEBUG("%s 0x%08" PRIx32 " %" PRIu32 " %" PRIu32, __func__, address, size, count); return adapter->layout->api->read_mem(adapter->fd, address, size, count, buffer); } @@ -777,7 +777,7 @@ static int adapter_write_memory(struct target *target, uint32_t address, if (!count || !buffer) return ERROR_COMMAND_SYNTAX_ERROR; - LOG_DEBUG("%s 0x%08x %d %d", __func__, address, size, count); + LOG_DEBUG("%s 0x%08" PRIx32 " %" PRIu32 " %" PRIu32, __func__, address, size, count); return adapter->layout->api->write_mem(adapter->fd, address, size, count, buffer); } diff --git a/src/target/mips32.c b/src/target/mips32.c index c9cbf86e4..188e88bfc 100644 --- a/src/target/mips32.c +++ b/src/target/mips32.c @@ -825,7 +825,7 @@ COMMAND_HANDLER(mips32_handle_scan_delay_command) struct mips_ejtag *ejtag_info = &mips32->ejtag_info; if (CMD_ARGC == 1) - COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], ejtag_info->scan_delay); + COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], ejtag_info->scan_delay); else if (CMD_ARGC > 1) return ERROR_COMMAND_SYNTAX_ERROR; diff --git a/src/target/mips32_pracc.c b/src/target/mips32_pracc.c index d0ecba2fd..6a66aa9a2 100644 --- a/src/target/mips32_pracc.c +++ b/src/target/mips32_pracc.c @@ -373,7 +373,7 @@ int mips32_pracc_queue_exec(struct mips_ejtag *ejtag_info, struct pracc_queue_in goto exit; } if (addr != store_addr) { - LOG_ERROR("Store address mismatch, read: %x expected: %x count: %d", + LOG_ERROR("Store address mismatch, read: %" PRIx32 " expected: %" PRIx32 " count: %d", addr, store_addr, scan_count); retval = ERROR_FAIL; goto exit; @@ -388,7 +388,8 @@ int mips32_pracc_queue_exec(struct mips_ejtag *ejtag_info, struct pracc_queue_in goto exit; } if (addr != fetch_addr) { - LOG_ERROR("Fetch addr mismatch, read: %x expected: %x count: %d", addr, fetch_addr, scan_count); + LOG_ERROR("Fetch addr mismatch, read: %" PRIx32 " expected: %" PRIx32 " count: %d", + addr, fetch_addr, scan_count); retval = ERROR_FAIL; goto exit; } diff --git a/src/target/mips_m4k.c b/src/target/mips_m4k.c index f4fd7d333..23b1767c6 100644 --- a/src/target/mips_m4k.c +++ b/src/target/mips_m4k.c @@ -147,7 +147,7 @@ static int mips_m4k_halt_smp(struct target *target) ret = mips_m4k_halt(curr); if (ret != ERROR_OK) { - LOG_ERROR("halt failed target->coreid: %d", curr->coreid); + LOG_ERROR("halt failed target->coreid: %" PRId32, curr->coreid); retval = ret; } head = head->next; @@ -405,7 +405,7 @@ static int mips_m4k_restore_smp(struct target *target, uint32_t address, int han handle_breakpoints, 0); if (ret != ERROR_OK) { - LOG_ERROR("target->coreid :%d failed to resume at address :0x%x", + LOG_ERROR("target->coreid :%" PRId32 " failed to resume at address :0x%" PRIx32, curr->coreid, address); retval = ret; } @@ -602,7 +602,7 @@ static int mips_m4k_set_breakpoint(struct target *target, while (comparator_list[bp_num].used && (bp_num < mips32->num_inst_bpoints)) bp_num++; if (bp_num >= mips32->num_inst_bpoints) { - LOG_ERROR("Can not find free FP Comparator(bpid: %d)", + LOG_ERROR("Can not find free FP Comparator(bpid: %" PRIu32 ")", breakpoint->unique_id); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } @@ -622,11 +622,11 @@ static int mips_m4k_set_breakpoint(struct target *target, ejtag_info->ejtag_ibm_offs, 0x00000000); target_write_u32(target, comparator_list[bp_num].reg_address + ejtag_info->ejtag_ibc_offs, 1); - LOG_DEBUG("bpid: %d, bp_num %i bp_value 0x%" PRIx32 "", + LOG_DEBUG("bpid: %" PRIu32 ", bp_num %i bp_value 0x%" PRIx32 "", breakpoint->unique_id, bp_num, comparator_list[bp_num].bp_value); } else if (breakpoint->type == BKPT_SOFT) { - LOG_DEBUG("bpid: %d", breakpoint->unique_id); + LOG_DEBUG("bpid: %" PRIu32, breakpoint->unique_id); if (breakpoint->length == 4) { uint32_t verify = 0xffffffff; @@ -690,11 +690,11 @@ static int mips_m4k_unset_breakpoint(struct target *target, if (breakpoint->type == BKPT_HARD) { int bp_num = breakpoint->set - 1; if ((bp_num < 0) || (bp_num >= mips32->num_inst_bpoints)) { - LOG_DEBUG("Invalid FP Comparator number in breakpoint (bpid: %d)", + LOG_DEBUG("Invalid FP Comparator number in breakpoint (bpid: %" PRIu32 ")", breakpoint->unique_id); return ERROR_OK; } - LOG_DEBUG("bpid: %d - releasing hw: %d", + LOG_DEBUG("bpid: %" PRIu32 " - releasing hw: %d", breakpoint->unique_id, bp_num); comparator_list[bp_num].used = 0; @@ -704,7 +704,7 @@ static int mips_m4k_unset_breakpoint(struct target *target, } else { /* restore original instruction (kept in target endianness) */ - LOG_DEBUG("bpid: %d", breakpoint->unique_id); + LOG_DEBUG("bpid: %" PRIu32, breakpoint->unique_id); if (breakpoint->length == 4) { uint32_t current_instr; @@ -1296,7 +1296,7 @@ COMMAND_HANDLER(mips_m4k_handle_smp_gdb_command) target->gdb_service->core[1] = coreid; } - command_print(CMD_CTX, "gdb coreid %d -> %d", target->gdb_service->core[0] + command_print(CMD_CTX, "gdb coreid %" PRId32 " -> %" PRId32, target->gdb_service->core[0] , target->gdb_service->core[1]); } return ERROR_OK; @@ -1309,7 +1309,7 @@ COMMAND_HANDLER(mips_m4k_handle_scan_delay_command) struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info; if (CMD_ARGC == 1) - COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], ejtag_info->scan_delay); + COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], ejtag_info->scan_delay); else if (CMD_ARGC > 1) return ERROR_COMMAND_SYNTAX_ERROR; diff --git a/src/target/nds32.c b/src/target/nds32.c index b171afebe..d2e877215 100644 --- a/src/target/nds32.c +++ b/src/target/nds32.c @@ -86,7 +86,7 @@ static int nds32_get_core_reg(struct reg *reg) } if (reg->valid) { - LOG_DEBUG("reading register(cached) %i(%s), value: 0x%8.8" PRIx32, + LOG_DEBUG("reading register(cached) %" PRIi32 "(%s), value: 0x%8.8" PRIx32, reg_arch_info->num, reg->name, reg_arch_info->value); return ERROR_OK; } @@ -110,7 +110,7 @@ static int nds32_get_core_reg(struct reg *reg) mapped_regnum, &(reg_arch_info->value)); } - LOG_DEBUG("reading register %i(%s), value: 0x%8.8" PRIx32, + LOG_DEBUG("reading register %" PRIi32 "(%s), value: 0x%8.8" PRIx32, reg_arch_info->num, reg->name, reg_arch_info->value); } @@ -309,7 +309,7 @@ static int nds32_set_core_reg(struct reg *reg, uint8_t *buf) if (nds32_reg_exception(mapped_regnum, value)) return ERROR_OK; - LOG_DEBUG("writing register %i(%s) with value 0x%8.8" PRIx32, + LOG_DEBUG("writing register %" PRIi32 "(%s) with value 0x%8.8" PRIx32, reg_arch_info->num, reg->name, value); if ((nds32->fpu_enable == false) && @@ -1572,7 +1572,7 @@ int nds32_edm_config(struct nds32 *nds32) aice_read_debug_reg(aice, NDS_EDM_SR_EDM_CFG, &edm_cfg); nds32->edm.version = (edm_cfg >> 16) & 0xFFFF; - LOG_INFO("EDM version 0x%04" PRIx32, nds32->edm.version); + LOG_INFO("EDM version 0x%04x", nds32->edm.version); nds32->edm.breakpoint_num = (edm_cfg & 0x7) + 1; @@ -2008,7 +2008,7 @@ int nds32_login(struct nds32 *nds32) code_str[copy_length] = '\0'; code = strtoul(code_str, NULL, 16); - sprintf(command_str, "write_misc gen_port0 0x%x;", code); + sprintf(command_str, "write_misc gen_port0 0x%" PRIx32 ";", code); strcat(command_sequence, command_str); } @@ -2033,7 +2033,7 @@ int nds32_login(struct nds32 *nds32) else return ERROR_FAIL; - sprintf(command_str, "write_misc %s 0x%x;", reg_name, code); + sprintf(command_str, "write_misc %s 0x%" PRIx32 ";", reg_name, code); if (ERROR_OK != aice_program_edm(aice, command_str)) return ERROR_FAIL; } @@ -2118,7 +2118,7 @@ int nds32_poll(struct target *target) int nds32_resume(struct target *target, int current, uint32_t address, int handle_breakpoints, int debug_execution) { - LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d", + LOG_DEBUG("current %d address %08" PRIx32 " handle_breakpoints %d debug_execution %d", current, address, handle_breakpoints, debug_execution); struct nds32 *nds32 = target_to_nds32(target); @@ -2219,7 +2219,7 @@ int nds32_assert_reset(struct target *target) static int nds32_gdb_attach(struct nds32 *nds32) { - LOG_DEBUG("nds32_gdb_attach, target coreid: %d", nds32->target->coreid); + LOG_DEBUG("nds32_gdb_attach, target coreid: %" PRId32, nds32->target->coreid); if (nds32->attached == false) { @@ -2318,7 +2318,7 @@ int nds32_get_gdb_fileio_info(struct target *target, struct gdb_fileio_info *fil syscall_id = (value_ir6 >> 16) & 0x7FFF; nds32->active_syscall_id = syscall_id; - LOG_DEBUG("hit syscall ID: 0x%x", syscall_id); + LOG_DEBUG("hit syscall ID: 0x%" PRIx32, syscall_id); /* free previous identifier storage */ if (NULL != fileio_info->identifier) { diff --git a/src/target/nds32_cmd.c b/src/target/nds32_cmd.c index c11df37af..8970fd7ee 100644 --- a/src/target/nds32_cmd.c +++ b/src/target/nds32_cmd.c @@ -816,7 +816,7 @@ static int jim_nds32_bulk_read(Jim_Interp *interp, int argc, Jim_Obj * const *ar jim_wide i; Jim_SetResult(interp, Jim_NewEmptyStringObj(interp)); for (i = 0; i < count; i++) { - sprintf(data_str, "0x%08x ", data[i]); + sprintf(data_str, "0x%08" PRIx32 " ", data[i]); Jim_AppendStrings(interp, Jim_GetResult(interp), data_str, NULL); } @@ -864,7 +864,7 @@ static int jim_nds32_read_edm_sr(Jim_Interp *interp, int argc, Jim_Obj * const * aice_read_debug_reg(aice, edm_sr_number, &edm_sr_value); - sprintf(data_str, "0x%08x", edm_sr_value); + sprintf(data_str, "0x%08" PRIx32, edm_sr_value); Jim_SetResult(interp, Jim_NewEmptyStringObj(interp)); Jim_AppendStrings(interp, Jim_GetResult(interp), data_str, NULL); diff --git a/src/target/nds32_reg.c b/src/target/nds32_reg.c index 72ac4798c..997f4ed39 100644 --- a/src/target/nds32_reg.c +++ b/src/target/nds32_reg.c @@ -369,7 +369,7 @@ bool nds32_reg_exception(uint32_t number, uint32_t value) field_value = (value >> ex_reg_value->ex_value_bit_pos) & ex_reg_value->ex_value_mask; if (field_value == ex_reg_value->ex_value) { - LOG_WARNING("It will generate exceptions as setting %d to %s", + LOG_WARNING("It will generate exceptions as setting %" PRId32 " to %s", value, nds32_regs[number].simple_mnemonic); return true; } diff --git a/src/target/target.c b/src/target/target.c index 942dbc1c3..d78f3b160 100644 --- a/src/target/target.c +++ b/src/target/target.c @@ -1796,7 +1796,7 @@ static int target_profiling_default(struct target *target, uint32_t *samples, gettimeofday(&now, NULL); if ((sample_count >= max_num_samples) || ((now.tv_sec >= timeout.tv_sec) && (now.tv_usec >= timeout.tv_usec))) { - LOG_INFO("Profiling completed. %d samples.", sample_count); + LOG_INFO("Profiling completed. %" PRIu32 " samples.", sample_count); break; } } @@ -3541,7 +3541,7 @@ COMMAND_HANDLER(handle_profile_command) return ERROR_FAIL; } - COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], offset); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], offset); /** * Some cores let us sample the PC without the @@ -3581,8 +3581,8 @@ COMMAND_HANDLER(handle_profile_command) bool with_range = false; if (CMD_ARGC == 4) { with_range = true; - COMMAND_PARSE_NUMBER(uint, CMD_ARGV[2], start_address); - COMMAND_PARSE_NUMBER(uint, CMD_ARGV[3], end_address); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], start_address); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[3], end_address); } write_gmon(samples, num_of_sampels, CMD_ARGV[1], @@ -5439,7 +5439,7 @@ COMMAND_HANDLER(handle_fast_load_image_command) fastload[i].data = malloc(length); if (fastload[i].data == NULL) { free(buffer); - command_print(CMD_CTX, "error allocating buffer for section (%d bytes)", + command_print(CMD_CTX, "error allocating buffer for section (%" PRIu32 " bytes)", length); retval = ERROR_FAIL; break; diff --git a/src/target/xscale.c b/src/target/xscale.c index 3371a65d3..388c8eb51 100644 --- a/src/target/xscale.c +++ b/src/target/xscale.c @@ -3388,7 +3388,7 @@ COMMAND_HANDLER(xscale_handle_trace_buffer_command) if (xscale->trace.mode != XSCALE_TRACE_DISABLED) { char fill_string[12]; - sprintf(fill_string, "fill %" PRId32, xscale->trace.buffer_fill); + sprintf(fill_string, "fill %d", xscale->trace.buffer_fill); command_print(CMD_CTX, "trace buffer enabled (%s)", (xscale->trace.mode == XSCALE_TRACE_FILL) ? fill_string : "wrap");