ADIv5 header cleanup (+ #defines)
Update the comments about DP registers and some of the bitfields. Remove inappropriate (and unused) DP_ZERO declaration. Add some (currently unused) #defines needed for SWD protocol support, based on previous patches from Andreas Fritiofson and Simon Qian. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>__archive__
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@ -42,22 +42,42 @@
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#define JTAG_ACK_OK_FAULT 0x2
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#define JTAG_ACK_OK_FAULT 0x2
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#define JTAG_ACK_WAIT 0x1
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#define JTAG_ACK_WAIT 0x1
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/* three-bit ACK values for SWD access (sent LSB first) */
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#define SWD_ACK_OK 0x4
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#define SWD_ACK_WAIT 0x2
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#define SWD_ACK_FAULT 0x1
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#define DPAP_WRITE 0
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#define DPAP_WRITE 0
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#define DPAP_READ 1
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#define DPAP_READ 1
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/* A[3:0] for DP registers (for JTAG, stored in DPACC) */
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/* A[3:0] for DP registers; A[1:0] are always zero.
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#define DP_ZERO 0
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* - JTAG accesses all of these via JTAG_DP_DPACC, except for
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#define DP_CTRL_STAT 0x4
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* IDCODE (JTAG_DP_IDCODE) and ABORT (JTAG_DP_ABORT).
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#define DP_SELECT 0x8
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* - SWD accesses these directly, sometimes needing SELECT.CTRLSEL
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#define DP_RDBUFF 0xC
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*/
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#define DP_IDCODE 0 /* SWD: read */
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#define DP_ABORT 0 /* SWD: write */
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#define DP_CTRL_STAT 0x4 /* r/w */
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#define DP_WCR 0x4 /* SWD: r/w (mux CTRLSEL) */
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#define DP_RESEND 0x8 /* SWD: read */
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#define DP_SELECT 0x8 /* JTAG: r/w; SWD: write */
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#define DP_RDBUFF 0xC /* read-only */
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/* Fields of the DP's AP ABORT register */
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#define DAPABORT (1 << 0)
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#define STKCMPCLR (1 << 1) /* SWD-only */
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#define STKERRCLR (1 << 2) /* SWD-only */
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#define WDERRCLR (1 << 3) /* SWD-only */
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#define ORUNERRCLR (1 << 4) /* SWD-only */
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/* Fields of the DP's CTRL/STAT register */
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/* Fields of the DP's CTRL/STAT register */
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#define CORUNDETECT (1 << 0)
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#define CORUNDETECT (1 << 0)
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#define SSTICKYORUN (1 << 1)
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#define SSTICKYORUN (1 << 1)
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/* 3:2 - transaction mode (e.g. pushed compare) */
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/* 3:2 - transaction mode (e.g. pushed compare) */
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#define SSTICKYCMP (1 << 4)
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#define SSTICKYERR (1 << 5)
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#define SSTICKYERR (1 << 5)
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#define READOK (1 << 6)
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#define READOK (1 << 6) /* SWD-only */
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#define WDATAERR (1 << 7)
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#define WDATAERR (1 << 7) /* SWD-only */
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/* 11:8 - mask lanes for pushed compare or verify ops */
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/* 11:8 - mask lanes for pushed compare or verify ops */
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/* 21:12 - transaction counter */
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/* 21:12 - transaction counter */
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#define CDBGRSTREQ (1 << 26)
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#define CDBGRSTREQ (1 << 26)
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