tcl/board: add board configuration for NXP IMX7SABRE
configuration also contains a reset-init procedure that disables the watchdog and initilizes the boards DDR memory so that you can upload baremetal (e.g. boot loader) code into DDR and start it from there. Change-Id: I4d2311b3708a5fcb5174a3447f34ae3904de7243 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4227 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>riscv-compliance-dev^2
Matthias Welwarsky
Tim Newsome
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# NXP IMX7SABRE board
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# use on-board JTAG header
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transport select jtag
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# set a safe speed, can be overridden
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adapter_khz 1000
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# reset configuration has TRST and SRST support
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reset_config trst_and_srst srst_push_pull
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# need at least 100ms delay after SRST release for JTAG
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adapter_nsrst_delay 100
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# source the target file
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source [find target/imx7.cfg]
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# import mrw proc
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source [find mem_helper.tcl]
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# function to disable the on-chip watchdog
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proc imx7_disable_wdog { } {
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# echo "disable watchdog power-down counter"
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mwh phys 0x30280008 0x00
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}
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proc imx7_uart_dbgconf { } {
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# disable response to debug_req signal for uart1
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mww phys 0x308600b4 0x0a60
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}
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proc check_bits_set_32 { addr mask } {
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while { [expr [mrw $addr] & $mask == 0] } { }
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}
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proc apply_dcd { } {
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# echo "apply dcd"
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mww phys 0x30340004 0x4F400005
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# Clear then set bit30 to ensure exit from DDR retention
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mww phys 0x30360388 0x40000000
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mww phys 0x30360384 0x40000000
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mww phys 0x30391000 0x00000002
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mww phys 0x307a0000 0x01040001
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mww phys 0x307a01a0 0x80400003
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mww phys 0x307a01a4 0x00100020
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mww phys 0x307a01a8 0x80100004
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mww phys 0x307a0064 0x00400046
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mww phys 0x307a0490 0x00000001
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mww phys 0x307a00d0 0x00020083
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mww phys 0x307a00d4 0x00690000
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mww phys 0x307a00dc 0x09300004
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mww phys 0x307a00e0 0x04080000
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mww phys 0x307a00e4 0x00100004
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mww phys 0x307a00f4 0x0000033f
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mww phys 0x307a0100 0x09081109
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mww phys 0x307a0104 0x0007020d
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mww phys 0x307a0108 0x03040407
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mww phys 0x307a010c 0x00002006
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mww phys 0x307a0110 0x04020205
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mww phys 0x307a0114 0x03030202
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mww phys 0x307a0120 0x00000803
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mww phys 0x307a0180 0x00800020
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mww phys 0x307a0184 0x02000100
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mww phys 0x307a0190 0x02098204
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mww phys 0x307a0194 0x00030303
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mww phys 0x307a0200 0x00000016
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mww phys 0x307a0204 0x00171717
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mww phys 0x307a0214 0x04040404
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mww phys 0x307a0218 0x0f040404
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mww phys 0x307a0240 0x06000604
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mww phys 0x307a0244 0x00000001
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mww phys 0x30391000 0x00000000
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mww phys 0x30790000 0x17420f40
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mww phys 0x30790004 0x10210100
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mww phys 0x30790010 0x00060807
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mww phys 0x307900b0 0x1010007e
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mww phys 0x3079009c 0x00000d6e
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mww phys 0x30790020 0x08080808
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mww phys 0x30790030 0x08080808
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mww phys 0x30790050 0x01000010
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mww phys 0x30790050 0x00000010
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mww phys 0x307900c0 0x0e407304
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mww phys 0x307900c0 0x0e447304
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mww phys 0x307900c0 0x0e447306
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check_bits_set_32 0x307900c4 0x1
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mww phys 0x307900c0 0x0e447304
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mww phys 0x307900c0 0x0e407304
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mww phys 0x30384130 0x00000000
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mww phys 0x30340020 0x00000178
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mww phys 0x30384130 0x00000002
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mww phys 0x30790018 0x0000000f
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check_bits_set_32 0x307a0004 0x1
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}
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# disable internal reset-assert handling to
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# allow reset-init to work
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$_TARGETNAME.0 configure -event reset-assert ""
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$_TARGETNAME.1 configure -event reset-assert ""
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$_TARGETNAME_2 configure -event reset-assert ""
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$_TARGETNAME.0 configure -event reset-init {
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global _CHIPNAME
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imx7_disable_wdog
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imx7_uart_dbgconf
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apply_dcd
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$_CHIPNAME.dap memaccess 0
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}
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target smp $_TARGETNAME.0 $_TARGETNAME.1
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