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armv7a_mmu: Do not restrict virtual addresses to uint32_t 

In preparation for adding super section decoding, do not restrict
armv7a_mmu_translate_va_pa() to 32-bit virtual addresses since ARMv7-A
processors with VMSA extensions (including LPAE) can issue wider
physical addresses. Update casting to uint32_t where necessary.

Change-Id: Id1c3d0d5ac324cbdc334259d9ea75fe4981671a1
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Reviewed-on: http://openocd.zylin.com/5211
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
bscan_optimization
Florian Fainelli 2019-03-19 09:50:41 -07:00 committed by Matthias Welwarsky
parent 604dded6f1
commit eeabbd58c0
3 changed files with 7 additions and 6 deletions
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9
src/target/armv7a_mmu.c
View File

@ -36,12 +36,12 @@
/* V7 method VA TO PA */ /* V7 method VA TO PA */
int armv7a_mmu_translate_va_pa(struct target *target, uint32_t va, int armv7a_mmu_translate_va_pa(struct target *target, uint32_t va,
uint32_t *val, int meminfo) target_addr_t *val, int meminfo)
{ {
int retval = ERROR_FAIL; int retval = ERROR_FAIL;
struct armv7a_common *armv7a = target_to_armv7a(target); struct armv7a_common *armv7a = target_to_armv7a(target);
struct arm_dpm *dpm = armv7a->arm.dpm; struct arm_dpm *dpm = armv7a->arm.dpm;
uint32_t virt = va & ~0xfff; uint32_t virt = va & ~0xfff, value;
uint32_t NOS, NS, INNER, OUTER; uint32_t NOS, NS, INNER, OUTER;
*val = 0xdeadbeef; *val = 0xdeadbeef;
retval = dpm->prepare(dpm); retval = dpm->prepare(dpm);
@ -56,9 +56,10 @@ int armv7a_mmu_translate_va_pa(struct target *target, uint32_t va,
goto done; goto done;
retval = dpm->instr_read_data_r0(dpm, retval = dpm->instr_read_data_r0(dpm,
ARMV4_5_MRC(15, 0, 0, 7, 4, 0), ARMV4_5_MRC(15, 0, 0, 7, 4, 0),
val); &value);
if (retval != ERROR_OK) if (retval != ERROR_OK)
goto done; goto done;
*val = value;
/* decode memory attribute */ /* decode memory attribute */
NOS = (*val >> 10) & 1; /* Not Outer shareable */ NOS = (*val >> 10) & 1; /* Not Outer shareable */
NS = (*val >> 9) & 1; /* Non secure */ NS = (*val >> 9) & 1; /* Non secure */
@ -67,7 +68,7 @@ int armv7a_mmu_translate_va_pa(struct target *target, uint32_t va,
*val = (*val & ~0xfff) + (va & 0xfff); *val = (*val & ~0xfff) + (va & 0xfff);
if (meminfo) { if (meminfo) {
LOG_INFO("%" PRIx32 " : %" PRIx32 " %s outer shareable %s secured", LOG_INFO("%" PRIx32 " : %" TARGET_PRIxADDR " %s outer shareable %s secured",
va, *val, va, *val,
NOS == 1 ? "not" : " ", NOS == 1 ? "not" : " ",
NS == 1 ? "not" : ""); NS == 1 ? "not" : "");

2
src/target/armv7a_mmu.h
View File

@ -20,7 +20,7 @@
#define OPENOCD_TARGET_ARMV7A_MMU_H #define OPENOCD_TARGET_ARMV7A_MMU_H
extern int armv7a_mmu_translate_va_pa(struct target *target, uint32_t va, extern int armv7a_mmu_translate_va_pa(struct target *target, uint32_t va,
uint32_t *val, int meminfo); target_addr_t *val, int meminfo);
extern const struct command_registration armv7a_mmu_command_handlers[]; extern const struct command_registration armv7a_mmu_command_handlers[];

2
src/target/cortex_a.c
View File

@ -2922,7 +2922,7 @@ static int cortex_a_virt2phys(struct target *target,
if (retval != ERROR_OK) if (retval != ERROR_OK)
return retval; return retval;
return armv7a_mmu_translate_va_pa(target, (uint32_t)virt, return armv7a_mmu_translate_va_pa(target, (uint32_t)virt,
(uint32_t *)phys, 1); phys, 1);
} }
COMMAND_HANDLER(cortex_a_handle_cache_info_command) COMMAND_HANDLER(cortex_a_handle_cache_info_command)