ARM11: use standard run_algorithm()
As with single stepping, the previous stuff was needed because the ARM11 code wasn't using the standard ARM base type and register access ... but now those mechanisms work, so we can switch out that special-purpose glue, in favor of the more thoroughly tested/capable "standard" code. Fixes a bug in the resume() implementation: it wasn't handling two of its arguments correctly, preventing the "flash erase_check" algorithm from working. (This code needs a *subsequent* update for correct register handling, though... removing the confusion about which "r2", for example, to use.) This should resolve some "FIXME" comments too, for Thumb and processor mode support. It also gets rid of a nasty exit() call; servers should only have *clean* shutdown paths. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>__archive__
David Brownell
parent
bf3abc48f0
commit
ec64acf536
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@ -665,8 +665,11 @@ static int arm11_resume(struct target *target, int current,
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/* clear breakpoints/watchpoints and VCR*/
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arm11_sc7_clear_vbw(arm11);
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/* Set up breakpoints */
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if (!debug_execution)
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target_free_all_working_areas(target);
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/* Set up breakpoints */
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if (handle_breakpoints)
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{
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/* check if one matches PC and step over it if necessary */
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@ -1325,176 +1328,6 @@ static int arm11_remove_watchpoint(struct target *target,
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return ERROR_FAIL;
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}
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// HACKHACKHACK - FIXME mode/state
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/* target algorithm support */
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static int arm11_run_algorithm(struct target *target,
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int num_mem_params, struct mem_param *mem_params,
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int num_reg_params, struct reg_param *reg_params,
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uint32_t entry_point, uint32_t exit_point,
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int timeout_ms, void *arch_info)
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{
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struct arm11_common *arm11 = target_to_arm11(target);
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// enum armv4_5_state core_state = arm11->core_state;
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// enum armv4_5_mode core_mode = arm11->core_mode;
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uint32_t context[16];
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uint32_t cpsr;
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int exit_breakpoint_size = 0;
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int retval = ERROR_OK;
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LOG_DEBUG("Running algorithm");
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if (target->state != TARGET_HALTED)
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{
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LOG_WARNING("target not halted");
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return ERROR_TARGET_NOT_HALTED;
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}
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// FIXME
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// if (!is_arm_mode(arm11->core_mode))
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// return ERROR_FAIL;
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// Save regs
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for (unsigned i = 0; i < 16; i++)
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{
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context[i] = buf_get_u32((uint8_t*)(&arm11->reg_values[i]),0,32);
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LOG_DEBUG("Save %u: 0x%" PRIx32 "", i, context[i]);
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}
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cpsr = buf_get_u32((uint8_t*)(arm11->reg_values + ARM11_RC_CPSR),0,32);
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LOG_DEBUG("Save CPSR: 0x%" PRIx32 "", cpsr);
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for (int i = 0; i < num_mem_params; i++)
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{
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target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
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}
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// Set register parameters
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for (int i = 0; i < num_reg_params; i++)
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{
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struct reg *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
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if (!reg)
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{
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LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
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return ERROR_INVALID_ARGUMENTS;
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}
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if (reg->size != reg_params[i].size)
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{
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LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
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return ERROR_INVALID_ARGUMENTS;
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}
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arm11_set_reg(reg,reg_params[i].value);
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// printf("%i: Set %s =%08x\n", i, reg_params[i].reg_name,val);
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}
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exit_breakpoint_size = 4;
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/* arm11->core_state = arm11_algorithm_info->core_state;
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if (arm11->core_state == ARMV4_5_STATE_ARM)
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exit_breakpoint_size = 4;
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else if (arm11->core_state == ARMV4_5_STATE_THUMB)
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exit_breakpoint_size = 2;
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else
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{
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LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
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exit(-1);
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}
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*/
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/* arm11 at this point only supports ARM not THUMB mode
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however if this test needs to be reactivated the current state can be read back
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from CPSR */
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#if 0
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if (arm11_algorithm_info->core_mode != ARMV4_5_MODE_ANY)
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{
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LOG_DEBUG("setting core_mode: 0x%2.2x", arm11_algorithm_info->core_mode);
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buf_set_u32(arm11->reg_list[ARM11_RC_CPSR].value, 0, 5, arm11_algorithm_info->core_mode);
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arm11->reg_list[ARM11_RC_CPSR].dirty = 1;
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arm11->reg_list[ARM11_RC_CPSR].valid = 1;
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}
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#endif
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if ((retval = breakpoint_add(target, exit_point, exit_breakpoint_size, BKPT_HARD)) != ERROR_OK)
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{
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LOG_ERROR("can't add breakpoint to finish algorithm execution");
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retval = ERROR_TARGET_FAILURE;
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goto restore;
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}
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// no debug, otherwise breakpoint is not set
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CHECK_RETVAL(target_resume(target, 0, entry_point, 1, 0));
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CHECK_RETVAL(target_wait_state(target, TARGET_HALTED, timeout_ms));
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if (target->state != TARGET_HALTED)
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{
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CHECK_RETVAL(target_halt(target));
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CHECK_RETVAL(target_wait_state(target, TARGET_HALTED, 500));
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retval = ERROR_TARGET_TIMEOUT;
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goto del_breakpoint;
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}
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if (buf_get_u32(arm11->reg_list[15].value, 0, 32) != exit_point)
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{
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LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "",
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buf_get_u32(arm11->reg_list[15].value, 0, 32));
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retval = ERROR_TARGET_TIMEOUT;
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goto del_breakpoint;
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}
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for (int i = 0; i < num_mem_params; i++)
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{
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if (mem_params[i].direction != PARAM_OUT)
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target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
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}
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for (int i = 0; i < num_reg_params; i++)
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{
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if (reg_params[i].direction != PARAM_OUT)
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{
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struct reg *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
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if (!reg)
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{
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LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
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retval = ERROR_INVALID_ARGUMENTS;
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goto del_breakpoint;
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}
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if (reg->size != reg_params[i].size)
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{
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LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
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retval = ERROR_INVALID_ARGUMENTS;
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goto del_breakpoint;
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}
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buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
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}
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}
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del_breakpoint:
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breakpoint_remove(target, exit_point);
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restore:
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// Restore context
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for (size_t i = 0; i < 16; i++)
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{
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LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "",
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arm11->reg_list[i].name, context[i]);
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arm11_set_reg(&arm11->reg_list[i], (uint8_t*)&context[i]);
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}
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LOG_DEBUG("restoring CPSR with value 0x%8.8" PRIx32 "", cpsr);
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arm11_set_reg(&arm11->reg_list[ARM11_RC_CPSR], (uint8_t*)&cpsr);
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// arm11->core_state = core_state;
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// arm11->core_mode = core_mode;
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return retval;
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}
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static int arm11_target_create(struct target *target, Jim_Interp *interp)
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{
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struct arm11_common *arm11;
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@ -1925,7 +1758,7 @@ struct target_type arm11_target = {
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.add_watchpoint = arm11_add_watchpoint,
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.remove_watchpoint = arm11_remove_watchpoint,
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.run_algorithm = arm11_run_algorithm,
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.run_algorithm = armv4_5_run_algorithm,
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.register_commands = arm11_register_commands,
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.target_create = arm11_target_create,
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