Merge pull request #198 from riscv/hartsellen
Detect hartsellen, limiting which harts we probecompliance_dev
Tim Newsome
GitHub
commit
ec543bdc7b
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@ -441,12 +441,6 @@
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#define CSR_MCONTROL_M_LENGTH 1
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#define CSR_MCONTROL_M (0x1ULL << CSR_MCONTROL_M_OFFSET)
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/*
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* When set, enable this trigger in H mode.
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*/
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#define CSR_MCONTROL_H_OFFSET 5
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#define CSR_MCONTROL_H_LENGTH 1
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#define CSR_MCONTROL_H (0x1ULL << CSR_MCONTROL_H_OFFSET)
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/*
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* When set, enable this trigger in S mode.
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*/
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#define CSR_MCONTROL_S_OFFSET 4
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@ -487,7 +481,7 @@
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/*
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* When count is decremented to 0, the trigger fires. Instead of
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* changing \Fcount from 1 to 0, it is also acceptable for hardware to
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* clear \Fm, \Fh, \Fs, and \Fu. This allows \Fcount to be hard-wired
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* clear \Fm, \Fs, and \Fu. This allows \Fcount to be hard-wired
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* to 1 if this register just exists for single step.
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*/
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#define CSR_ICOUNT_COUNT_OFFSET 10
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@ -501,13 +495,6 @@
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#define CSR_ICOUNT_M_LENGTH 1
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#define CSR_ICOUNT_M (0x1ULL << CSR_ICOUNT_M_OFFSET)
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/*
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* When set, every instruction completed or exception taken in in H mode decrements \Fcount
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* by 1.
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*/
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#define CSR_ICOUNT_H_OFFSET 8
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#define CSR_ICOUNT_H_LENGTH 1
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#define CSR_ICOUNT_H (0x1ULL << CSR_ICOUNT_H_OFFSET)
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/*
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* When set, every instruction completed or exception taken in S mode decrements \Fcount
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* by 1.
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*/
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@ -544,19 +531,6 @@
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#define CSR_ICOUNT_ACTION (0x3fULL << CSR_ICOUNT_ACTION_OFFSET)
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#define DMI_DMSTATUS 0x11
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/*
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* Gets set if the Debug Module was accessed incorrectly.
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*
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* 0 (none): No error.
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*
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* 1 (badaddr): There was an access to an unimplemented Debug Module
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* address.
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*
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* 7 (other): An access failed for another reason.
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*/
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#define DMI_DMSTATUS_DMERR_OFFSET 24
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#define DMI_DMSTATUS_DMERR_LENGTH 3
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#define DMI_DMSTATUS_DMERR (0x7U << DMI_DMSTATUS_DMERR_OFFSET)
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/*
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* If 1, then there is an implicit {\tt ebreak} instruction at the
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* non-existent word immediately after the Program Buffer. This saves
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* the debugger from having to write the {\tt ebreak} itself, and
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@ -700,7 +674,7 @@
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*/
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#define DMI_DMCONTROL_HALTREQ_OFFSET 31
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#define DMI_DMCONTROL_HALTREQ_LENGTH 1
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#define DMI_DMCONTROL_HALTREQ (0x1U << DMI_DMCONTROL_HALTREQ_OFFSET)
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#define DMI_DMCONTROL_HALTREQ (0x1ULL << DMI_DMCONTROL_HALTREQ_OFFSET)
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/*
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* Writes the resume request bit for all currently selected harts.
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* When set to 1, each selected hart will resume if it is currently
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@ -713,7 +687,7 @@
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*/
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#define DMI_DMCONTROL_RESUMEREQ_OFFSET 30
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#define DMI_DMCONTROL_RESUMEREQ_LENGTH 1
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#define DMI_DMCONTROL_RESUMEREQ (0x1U << DMI_DMCONTROL_RESUMEREQ_OFFSET)
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#define DMI_DMCONTROL_RESUMEREQ (0x1ULL << DMI_DMCONTROL_RESUMEREQ_OFFSET)
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/*
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* This optional field writes the reset bit for all the currently
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* selected harts. To perform a reset the debugger writes 1, and then
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@ -727,7 +701,7 @@
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*/
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#define DMI_DMCONTROL_HARTRESET_OFFSET 29
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#define DMI_DMCONTROL_HARTRESET_LENGTH 1
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#define DMI_DMCONTROL_HARTRESET (0x1U << DMI_DMCONTROL_HARTRESET_OFFSET)
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#define DMI_DMCONTROL_HARTRESET (0x1ULL << DMI_DMCONTROL_HARTRESET_OFFSET)
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/*
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* Writing 1 to this bit clears the {\tt havereset} bits for
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* any selected harts.
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@ -736,7 +710,7 @@
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*/
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#define DMI_DMCONTROL_ACKHAVERESET_OFFSET 28
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#define DMI_DMCONTROL_ACKHAVERESET_LENGTH 1
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#define DMI_DMCONTROL_ACKHAVERESET (0x1U << DMI_DMCONTROL_ACKHAVERESET_OFFSET)
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#define DMI_DMCONTROL_ACKHAVERESET (0x1ULL << DMI_DMCONTROL_ACKHAVERESET_OFFSET)
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/*
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* Selects the definition of currently selected harts.
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*
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@ -752,14 +726,14 @@
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*/
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#define DMI_DMCONTROL_HASEL_OFFSET 26
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#define DMI_DMCONTROL_HASEL_LENGTH 1
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#define DMI_DMCONTROL_HASEL (0x1U << DMI_DMCONTROL_HASEL_OFFSET)
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#define DMI_DMCONTROL_HASEL (0x1ULL << DMI_DMCONTROL_HASEL_OFFSET)
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/*
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* The DM-specific index of the hart to select. This hart is always part of the
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* currently selected harts.
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*/
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#define DMI_DMCONTROL_HARTSEL_OFFSET 16
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#define DMI_DMCONTROL_HARTSEL_LENGTH 10
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#define DMI_DMCONTROL_HARTSEL (0x3ffU << DMI_DMCONTROL_HARTSEL_OFFSET)
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#define DMI_DMCONTROL_HARTSEL_LENGTH HARTSELLEN
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#define DMI_DMCONTROL_HARTSEL (((1L<<HARTSELLEN)-1) << DMI_DMCONTROL_HARTSEL_OFFSET)
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/*
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* This bit controls the reset signal from the DM to the rest of the
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* system. The signal should reset every part of the system, including
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@ -771,7 +745,7 @@
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*/
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#define DMI_DMCONTROL_NDMRESET_OFFSET 1
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#define DMI_DMCONTROL_NDMRESET_LENGTH 1
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#define DMI_DMCONTROL_NDMRESET (0x1U << DMI_DMCONTROL_NDMRESET_OFFSET)
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#define DMI_DMCONTROL_NDMRESET (0x1ULL << DMI_DMCONTROL_NDMRESET_OFFSET)
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/*
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* This bit serves as a reset signal for the Debug Module itself.
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*
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@ -794,7 +768,7 @@
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*/
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#define DMI_DMCONTROL_DMACTIVE_OFFSET 0
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#define DMI_DMCONTROL_DMACTIVE_LENGTH 1
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#define DMI_DMCONTROL_DMACTIVE (0x1U << DMI_DMCONTROL_DMACTIVE_OFFSET)
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#define DMI_DMCONTROL_DMACTIVE (0x1ULL << DMI_DMCONTROL_DMACTIVE_OFFSET)
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#define DMI_HARTINFO 0x12
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/*
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* Number of {\tt dscratch} registers available for the debugger
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@ -822,6 +796,9 @@
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*
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* If \Fdataaccess is 1: Number of 32-bit words in the memory map
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* dedicated to shadowing the {\tt data} registers.
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*
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* Since there are at most 12 {\tt data} registers, the value in this
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* register must be 12 or smaller.
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*/
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#define DMI_HARTINFO_DATASIZE_OFFSET 12
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#define DMI_HARTINFO_DATASIZE_LENGTH 4
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@ -988,8 +965,8 @@
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* abstract command interface. Valid sizes are 0 - 12.
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*/
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#define DMI_ABSTRACTCS_DATACOUNT_OFFSET 0
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#define DMI_ABSTRACTCS_DATACOUNT_LENGTH 5
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#define DMI_ABSTRACTCS_DATACOUNT (0x1fU << DMI_ABSTRACTCS_DATACOUNT_OFFSET)
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#define DMI_ABSTRACTCS_DATACOUNT_LENGTH 4
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#define DMI_ABSTRACTCS_DATACOUNT (0xfU << DMI_ABSTRACTCS_DATACOUNT_OFFSET)
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#define DMI_COMMAND 0x17
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/*
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* The type determines the overall functionality of this
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@ -1007,14 +984,14 @@
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#define DMI_COMMAND_CONTROL (0xffffffU << DMI_COMMAND_CONTROL_OFFSET)
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#define DMI_ABSTRACTAUTO 0x18
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/*
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* When a bit in this field is 1, read or write accesses the corresponding {\tt progbuf} word
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* When a bit in this field is 1, read or write accesses to the corresponding {\tt progbuf} word
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* cause the command in \Rcommand to be executed again.
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*/
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#define DMI_ABSTRACTAUTO_AUTOEXECPROGBUF_OFFSET 16
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#define DMI_ABSTRACTAUTO_AUTOEXECPROGBUF_LENGTH 16
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#define DMI_ABSTRACTAUTO_AUTOEXECPROGBUF (0xffffU << DMI_ABSTRACTAUTO_AUTOEXECPROGBUF_OFFSET)
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/*
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* When a bit in this field is 1, read or write accesses the corresponding {\tt data} word
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* When a bit in this field is 1, read or write accesses to the corresponding {\tt data} word
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* cause the command in \Rcommand to be executed again.
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*/
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#define DMI_ABSTRACTAUTO_AUTOEXECDATA_OFFSET 0
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@ -1041,17 +1018,59 @@
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#define DMI_AUTHDATA_DATA_OFFSET 0
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#define DMI_AUTHDATA_DATA_LENGTH 32
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#define DMI_AUTHDATA_DATA (0xffffffffU << DMI_AUTHDATA_DATA_OFFSET)
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#define DMI_SBADDRESS3 0x37
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/*
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* Accesses bits 127:96 of the physical address in {\tt sbaddress} (if
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* the system address bus is that wide).
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*/
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#define DMI_SBADDRESS3_ADDRESS_OFFSET 0
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#define DMI_SBADDRESS3_ADDRESS_LENGTH 32
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#define DMI_SBADDRESS3_ADDRESS (0xffffffffU << DMI_SBADDRESS3_ADDRESS_OFFSET)
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#define DMI_SBCS 0x38
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/*
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* When a 1 is written here, triggers a read at the address in {\tt
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* sbaddress} using the access size set by \Fsbaccess.
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* 0: The System Bus interface conforms to mainline drafts of this
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* spec older than 1 January, 2018.
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*
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* 1: The System Bus interface conforms to this version of the spec.
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*
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* Other values are reserved for future versions.
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*/
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#define DMI_SBCS_SBSINGLEREAD_OFFSET 20
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#define DMI_SBCS_SBSINGLEREAD_LENGTH 1
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#define DMI_SBCS_SBSINGLEREAD (0x1U << DMI_SBCS_SBSINGLEREAD_OFFSET)
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#define DMI_SBCS_SBVERSION_OFFSET 29
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#define DMI_SBCS_SBVERSION_LENGTH 3
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#define DMI_SBCS_SBVERSION (0x7U << DMI_SBCS_SBVERSION_OFFSET)
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/*
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* Select the access size to use for system bus accesses triggered by
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* writes to the {\tt sbaddress} registers or \Rsbdatazero.
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* Set when the debugger attempts to read data while a read is in
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* progress, or when the debugger initiates a new access while one is
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* already in progress (while \Fsbbusy is set). It remains set until
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* it's explicitly cleared by the debugger.
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*
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* While this field is non-zero, no more system bus accesses can be
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* initiated by the debug module.
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*/
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#define DMI_SBCS_SBBUSYERROR_OFFSET 22
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#define DMI_SBCS_SBBUSYERROR_LENGTH 1
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#define DMI_SBCS_SBBUSYERROR (0x1U << DMI_SBCS_SBBUSYERROR_OFFSET)
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/*
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* When 1, indicates the system bus master is busy. (Whether the
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* system bus itself is busy is related, but not the same thing.) This
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* bit goes high immediately when a read or write is requested for any
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* reason, and does not go low until the access is fully completed.
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*
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* To avoid race conditions, debuggers must not try to clear \Fsberror
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* until they read \Fsbbusy as 0.
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*/
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#define DMI_SBCS_SBBUSY_OFFSET 21
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#define DMI_SBCS_SBBUSY_LENGTH 1
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#define DMI_SBCS_SBBUSY (0x1U << DMI_SBCS_SBBUSY_OFFSET)
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/*
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* When 1, every write to \Rsbaddresszero automatically triggers a
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* system bus read at the new address.
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*/
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#define DMI_SBCS_SBREADONADDR_OFFSET 20
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#define DMI_SBCS_SBREADONADDR_LENGTH 1
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#define DMI_SBCS_SBREADONADDR (0x1U << DMI_SBCS_SBREADONADDR_OFFSET)
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/*
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* Select the access size to use for system bus accesses.
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*
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* 0: 8-bit
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*
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@ -1063,8 +1082,8 @@
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*
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* 4: 128-bit
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*
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* If an unsupported system bus access size is written here, the DM
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* does not perform the access and sberror is set to 3.
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* If \Fsbaccess has an unsupported value when the DM starts a bus
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* access, the access is not performed and \Fsberror is set to 3.
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*/
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#define DMI_SBCS_SBACCESS_OFFSET 17
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#define DMI_SBCS_SBACCESS_LENGTH 3
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@ -1080,9 +1099,9 @@
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* When 1, every read from \Rsbdatazero automatically triggers a
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* system bus read at the (possibly auto-incremented) address.
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*/
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#define DMI_SBCS_SBAUTOREAD_OFFSET 15
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#define DMI_SBCS_SBAUTOREAD_LENGTH 1
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#define DMI_SBCS_SBAUTOREAD (0x1U << DMI_SBCS_SBAUTOREAD_OFFSET)
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#define DMI_SBCS_SBREADONDATA_OFFSET 15
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#define DMI_SBCS_SBREADONDATA_LENGTH 1
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#define DMI_SBCS_SBREADONDATA (0x1U << DMI_SBCS_SBREADONDATA_OFFSET)
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/*
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* When the debug module's system bus
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* master causes a bus error, this field gets set. The bits in this
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@ -1097,10 +1116,6 @@
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* 2: A bad address was accessed.
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*
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* 3: There was some other error (eg. alignment).
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*
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* 4: The system bus master was busy when one of the
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* {\tt sbaddress} or {\tt sbdata} registers was written,
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* or \Rsbdatazero was read when it had stale data.
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*/
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#define DMI_SBCS_SBERROR_OFFSET 12
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#define DMI_SBCS_SBERROR_LENGTH 3
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@ -179,8 +179,23 @@ typedef struct {
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uint8_t datasize;
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uint8_t dataaccess;
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int16_t dataaddr;
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/* The width of the hartsel field. */
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unsigned hartsellen;
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} riscv013_info_t;
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static riscv013_info_t *get_info(const struct target *target)
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{
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riscv_info_t *info = (riscv_info_t *) target->arch_info;
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return (riscv013_info_t *) info->version_specific;
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}
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static uint32_t hartsel_mask(const struct target *target)
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{
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RISCV013_INFO(info);
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return ((1L<<info->hartsellen)-1) << DMI_DMCONTROL_HARTSEL_OFFSET;
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}
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static void decode_dmi(char *text, unsigned address, unsigned data)
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{
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static const struct {
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@ -192,7 +207,7 @@ static void decode_dmi(char *text, unsigned address, unsigned data)
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{ DMI_DMCONTROL, DMI_DMCONTROL_RESUMEREQ, "resumereq" },
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{ DMI_DMCONTROL, DMI_DMCONTROL_HARTRESET, "hartreset" },
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{ DMI_DMCONTROL, DMI_DMCONTROL_HASEL, "hasel" },
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{ DMI_DMCONTROL, DMI_DMCONTROL_HARTSEL, "hartsel" },
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{ DMI_DMCONTROL, ((1L<<10)-1) << DMI_DMCONTROL_HARTSEL_OFFSET, "hartsel" },
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{ DMI_DMCONTROL, DMI_DMCONTROL_NDMRESET, "ndmreset" },
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{ DMI_DMCONTROL, DMI_DMCONTROL_DMACTIVE, "dmactive" },
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@ -275,12 +290,6 @@ static void dump_field(const struct scan_field *field)
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}
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}
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static riscv013_info_t *get_info(const struct target *target)
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{
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riscv_info_t *info = (riscv_info_t *) target->arch_info;
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return (riscv013_info_t *) info->version_specific;
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}
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/*** Utility functions. ***/
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static void select_dmi(struct target *target)
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@ -1155,54 +1164,50 @@ static int examine(struct target *target)
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}
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/* Reset the Debug Module. */
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dmi_write(target, DMI_DMCONTROL, 0);
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dmi_write(target, DMI_DMCONTROL, DMI_DMCONTROL_DMACTIVE);
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uint32_t max_hartsel_mask = ((1L<<10)-1) << DMI_DMCONTROL_HARTSEL_OFFSET;
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dmi_write(target, DMI_DMCONTROL, max_hartsel_mask);
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dmi_write(target, DMI_DMCONTROL, max_hartsel_mask | DMI_DMCONTROL_DMACTIVE);
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uint32_t dmcontrol = dmi_read(target, DMI_DMCONTROL);
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uint32_t hartinfo = dmi_read(target, DMI_HARTINFO);
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LOG_DEBUG("dmcontrol: 0x%08x", dmcontrol);
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LOG_DEBUG("dmstatus: 0x%08x", dmstatus);
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LOG_DEBUG("hartinfo: 0x%08x", hartinfo);
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info->datasize = get_field(hartinfo, DMI_HARTINFO_DATASIZE);
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info->dataaccess = get_field(hartinfo, DMI_HARTINFO_DATAACCESS);
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info->dataaddr = get_field(hartinfo, DMI_HARTINFO_DATAADDR);
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if (!get_field(dmcontrol, DMI_DMCONTROL_DMACTIVE)) {
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LOG_ERROR("Debug Module did not become active. dmcontrol=0x%x",
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dmcontrol);
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return ERROR_FAIL;
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}
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uint32_t hartsel = get_field(dmcontrol, max_hartsel_mask);
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info->hartsellen = 0;
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while (hartsel & 1) {
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info->hartsellen++;
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hartsel >>= 1;
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}
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LOG_DEBUG("hartsellen=%d", info->hartsellen);
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uint32_t hartinfo = dmi_read(target, DMI_HARTINFO);
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info->datasize = get_field(hartinfo, DMI_HARTINFO_DATASIZE);
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info->dataaccess = get_field(hartinfo, DMI_HARTINFO_DATAACCESS);
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info->dataaddr = get_field(hartinfo, DMI_HARTINFO_DATAADDR);
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if (!get_field(dmstatus, DMI_DMSTATUS_AUTHENTICATED)) {
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LOG_ERROR("Authentication required by RISC-V core but not "
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"supported by OpenOCD. dmcontrol=0x%x", dmcontrol);
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return ERROR_FAIL;
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}
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if (get_field(dmstatus, DMI_DMSTATUS_ANYUNAVAIL)) {
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LOG_ERROR("The hart is unavailable.");
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return ERROR_FAIL;
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}
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if (get_field(dmstatus, DMI_DMSTATUS_ANYNONEXISTENT)) {
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LOG_ERROR("The hart doesn't exist.");
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return ERROR_FAIL;
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}
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/* Check that abstract data registers are accessible. */
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uint32_t abstractcs = dmi_read(target, DMI_ABSTRACTCS);
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info->datacount = get_field(abstractcs, DMI_ABSTRACTCS_DATACOUNT);
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info->progbufsize = get_field(abstractcs, DMI_ABSTRACTCS_PROGBUFSIZE);
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||||
|
||||
/* Before doing anything else we must first enumerate the harts. */
|
||||
RISCV_INFO(r);
|
||||
r->impebreak = get_field(dmstatus, DMI_DMSTATUS_IMPEBREAK);
|
||||
|
||||
/* Before doing anything else we must first enumerate the harts. */
|
||||
|
||||
/* Don't call any riscv_* functions until after we've counted the number of
|
||||
* cores and initialized registers. */
|
||||
for (int i = 0; i < RISCV_MAX_HARTS; ++i) {
|
||||
for (int i = 0; i < MIN(RISCV_MAX_HARTS, 1 << info->hartsellen); ++i) {
|
||||
if (!riscv_rtos_enabled(target) && i != target->coreid)
|
||||
continue;
|
||||
|
||||
|
|
@ -1248,6 +1253,11 @@ static int examine(struct target *target)
|
|||
|
||||
LOG_DEBUG("Enumerated %d harts", r->hart_count);
|
||||
|
||||
if (r->hart_count == 0) {
|
||||
LOG_ERROR("No harts found!");
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
|
||||
/* Then we check the number of triggers availiable to each hart. */
|
||||
riscv_enumerate_triggers(target);
|
||||
|
||||
|
|
@ -1297,7 +1307,7 @@ static int assert_reset(struct target *target)
|
|||
if (!riscv_hart_enabled(target, i))
|
||||
continue;
|
||||
|
||||
control = set_field(control_base, DMI_DMCONTROL_HARTSEL, i);
|
||||
control = set_field(control_base, hartsel_mask(target), i);
|
||||
control = set_field(control, DMI_DMCONTROL_HALTREQ,
|
||||
target->reset_halt ? 1 : 0);
|
||||
dmi_write(target, DMI_DMCONTROL, control);
|
||||
|
|
@ -1308,7 +1318,7 @@ static int assert_reset(struct target *target)
|
|||
|
||||
} else {
|
||||
/* Reset just this hart. */
|
||||
uint32_t control = set_field(control_base, DMI_DMCONTROL_HARTSEL,
|
||||
uint32_t control = set_field(control_base, hartsel_mask(target),
|
||||
r->current_hartid);
|
||||
control = set_field(control, DMI_DMCONTROL_HALTREQ,
|
||||
target->reset_halt ? 1 : 0);
|
||||
|
|
@ -1342,7 +1352,7 @@ static int deassert_reset(struct target *target)
|
|||
/* Clear the reset, but make sure haltreq is still set */
|
||||
uint32_t control = 0;
|
||||
control = set_field(control, DMI_DMCONTROL_HALTREQ, target->reset_halt ? 1 : 0);
|
||||
control = set_field(control, DMI_DMCONTROL_HARTSEL, r->current_hartid);
|
||||
control = set_field(control, hartsel_mask(target), r->current_hartid);
|
||||
control = set_field(control, DMI_DMCONTROL_DMACTIVE, 1);
|
||||
dmi_write(target, DMI_DMCONTROL, control);
|
||||
|
||||
|
|
@ -1948,7 +1958,7 @@ static void riscv013_select_current_hart(struct target *target)
|
|||
RISCV_INFO(r);
|
||||
|
||||
uint64_t dmcontrol = dmi_read(target, DMI_DMCONTROL);
|
||||
dmcontrol = set_field(dmcontrol, DMI_DMCONTROL_HARTSEL, r->current_hartid);
|
||||
dmcontrol = set_field(dmcontrol, hartsel_mask(target), r->current_hartid);
|
||||
dmi_write(target, DMI_DMCONTROL, dmcontrol);
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue