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balloon3 board base config 

This is the very basic board config for the balloon3 board cpu JTAG
channel.

The rest of the config comprises another 14 .cfg files which I suspect
openocd doesn't really want all of. I'm still not sure how to deal
with this. I'll post another mail/patch to discuss.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
__archive__
Wookey 2009-10-26 17:06:05 +00:00 committed by David Brownell
parent 592e021543
commit eaebc6cd69
1 changed files with 13 additions and 0 deletions
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13
tcl/board/balloon3-cpu.cfg Normal file
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# Config for balloon3 board, cpu JTAG port. http://balloonboard.org/
# The board has separate JTAG ports for cpu and CPLD/FPGA devices
# Chaining is done on IO interfaces if desired.
source [find target/pxa270.cfg]
# The board supports separate reset lines
# Override this in the interface config for parallel dongles
reset_config trst_and_srst separate
# flash bank <driver> <base> <size> <chip_width> <bus_width>
# 29LV650 64Mbit Flash
flash bank cfi 0x00000000 0x800000 2 2 0