WIP on performance improvement.
Also implement empty arch_state to prevent occasional startup crash.__archive__
Tim Newsome
parent
2d02e77bed
commit
eac8933b89
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@ -117,6 +117,13 @@ enum {
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};
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#define MAX_HWBPS 16
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#define DRAM_CACHE_SIZE 16
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struct memory_cache_line {
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uint32_t data;
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bool valid;
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bool dirty;
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};
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typedef struct {
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/* Number of address bits in the dbus register. */
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@ -130,15 +137,11 @@ typedef struct {
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dbus_op_t dbus_op;
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/* Number of words in Debug RAM. */
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unsigned int dramsize;
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/* Our local copy of Debug RAM. */
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uint32_t *dram;
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/* One bit for every word in dram. If the bit is set, then we're
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* confident that the value we have matches the one in actual Debug
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* RAM. */
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uint64_t dram_valid;
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uint32_t dcsr;
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uint32_t dpc;
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struct memory_cache_line dram_cache[DRAM_CACHE_SIZE];
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struct reg *reg_list;
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/* Single buffer that contains all register names, instead of calling
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* malloc for each register. Needs to be freed when reg_list is freed. */
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@ -279,7 +282,8 @@ static dbus_status_t dbus_scan(struct target *target, uint64_t *data_in,
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return buf_get_u64(in, DBUS_OP_START, DBUS_OP_SIZE);
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}
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static uint64_t dbus_read(struct target *target, uint16_t address, uint16_t next_address)
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static uint64_t dbus_read(struct target *target, uint16_t address,
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uint16_t next_address)
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{
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riscv_info_t *info = (riscv_info_t *) target->arch_info;
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uint64_t value;
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@ -338,38 +342,125 @@ static uint32_t dtminfo_read(struct target *target)
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static uint32_t dram_read32(struct target *target, unsigned int index)
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{
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riscv_info_t *info = (riscv_info_t *) target->arch_info;
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// TODO: check cache to see if this even needs doing.
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uint16_t address = dram_address(index);
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uint32_t value = dbus_read(target, address, address);
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info->dram_valid |= (1<<index);
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info->dram[index] = value;
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return value;
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}
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static void dram_write32(struct target *target, unsigned int index, uint32_t value,
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bool set_interrupt)
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{
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riscv_info_t *info = (riscv_info_t *) target->arch_info;
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#if 1
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if (!set_interrupt &&
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info->dram_valid & (1<<index) &&
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info->dram[index] == value) {
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LOG_DEBUG("DRAM cache hit: 0x%x @%d", value, index);
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return;
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}
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#endif
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uint64_t dbus_value = DMCONTROL_HALTNOT | value;
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if (set_interrupt)
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dbus_value |= DMCONTROL_INTERRUPT;
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dbus_write(target, dram_address(index), dbus_value);
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info->dram_valid |= (1<<index);
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info->dram[index] = value;
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}
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#if 1
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/** Read the haltnot and interrupt bits. */
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static bits_t read_bits(struct target *target)
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{
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riscv_info_t *info = (riscv_info_t *) target->arch_info;
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static int next_address = 0;
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uint64_t value;
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if (info->dbus_address < 0x10 || info->dbus_address == DMCONTROL) {
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value = dbus_read(target, info->dbus_address, next_address);
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} else {
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value = dbus_read(target, 0, next_address);
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}
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bits_t result = {
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.haltnot = get_field(value, DMCONTROL_HALTNOT),
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.interrupt = get_field(value, DMCONTROL_INTERRUPT)
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};
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return result;
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}
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static int wait_for_debugint_clear(struct target *target)
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{
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time_t start = time(NULL);
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// Throw away the results of the first read, since they'll contain the
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// result of the read that happened just before debugint was set. (Assuming
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// the last scan before calling this function was one that sets debugint.)
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read_bits(target);
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while (1) {
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bits_t bits = read_bits(target);
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if (!bits.interrupt) {
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return ERROR_OK;
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}
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if (time(NULL) - start > 2) {
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LOG_ERROR("Timed out waiting for debug int to clear.");
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return ERROR_FAIL;
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}
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}
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}
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static void cache_set(struct target *target, unsigned int index, uint32_t data)
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{
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riscv_info_t *info = (riscv_info_t *) target->arch_info;
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if (info->dram_cache[index].valid &&
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info->dram_cache[index].data == data) {
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// This is already preset on the target.
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LOG_DEBUG("Cache hit at 0x%x for data 0x%x", index, data);
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return;
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}
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info->dram_cache[index].data = data;
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info->dram_cache[index].valid = true;
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info->dram_cache[index].dirty = true;
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}
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static void cache_set_jump(struct target *target, unsigned int index)
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{
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cache_set(target, index,
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jal(0, (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*index))));
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}
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static void dump_debug_ram(struct target *target)
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{
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for (unsigned int i = 0; i < 16; i++) {
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uint32_t value = dram_read32(target, i);
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LOG_ERROR("Debug RAM 0x%x: 0x%08x", i, value);
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}
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}
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/** Run the program written to the debug RAM cache. */
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static int cache_run(struct target *target)
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{
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riscv_info_t *info = (riscv_info_t *) target->arch_info;
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unsigned int last = DRAM_CACHE_SIZE;
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for (unsigned int i = 0; i < DRAM_CACHE_SIZE; i++) {
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if (info->dram_cache[i].dirty) {
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last = i;
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break;
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}
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}
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if (last == DRAM_CACHE_SIZE) {
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// Nothing needs to be written to RAM.
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dram_write32(target, DMCONTROL, 0, true);
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} else {
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for (unsigned int i = 0; i < DRAM_CACHE_SIZE; i++) {
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if (i != last && info->dram_cache[i].dirty) {
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dram_write32(target, i, info->dram_cache[i].data, false);
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info->dram_cache[i].dirty = false;
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}
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}
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dram_write32(target, last, info->dram_cache[last].data, true);
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info->dram_cache[last].dirty = false;
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}
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if (wait_for_debugint_clear(target) != ERROR_OK) {
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LOG_ERROR("Debug interrupt didn't clear.");
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dump_debug_ram(target);
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return ERROR_FAIL;
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}
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return ERROR_OK;
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}
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#if 0
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static int dram_check32(struct target *target, unsigned int index,
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uint32_t expected)
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{
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@ -384,35 +475,6 @@ static int dram_check32(struct target *target, unsigned int index,
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}
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#endif
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/* Read the haltnot and interrupt bits. */
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static bits_t read_bits(struct target *target)
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{
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riscv_info_t *info = (riscv_info_t *) target->arch_info;
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static int next_address = 0;
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uint64_t value;
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if (info->dbus_address < 0x10 || info->dbus_address == DMCONTROL) {
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value = dbus_read(target, info->dbus_address, next_address);
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} else {
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value = dbus_read(target, 0, next_address);
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}
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if (info->dram_valid) {
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// Cycle through addresses, so we have more debug info. Only look at
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// ones that we've written, to reduce data mismatch between real life
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// and simulation.
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do {
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next_address = (next_address + 1) % 64;
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} while (!(info->dram_valid & (1<<next_address)));
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}
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bits_t result = {
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.haltnot = get_field(value, DMCONTROL_HALTNOT),
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.interrupt = get_field(value, DMCONTROL_INTERRUPT)
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};
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return result;
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}
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/* Write instruction that jumps from the specified word in Debug RAM to resume
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* in Debug ROM. */
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static void dram_write_jump(struct target *target, unsigned int index, bool set_interrupt)
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@ -440,25 +502,6 @@ static int wait_for_state(struct target *target, enum target_state state)
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}
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}
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static int wait_for_debugint_clear(struct target *target)
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{
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time_t start = time(NULL);
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// Throw away the results of the first read, since they'll contain the
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// result of the read that happened just before debugint was set. (Assuming
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// the last scan before calling this function was one that sets debugint.)
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read_bits(target);
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while (1) {
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bits_t bits = read_bits(target);
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if (!bits.interrupt) {
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return ERROR_OK;
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}
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if (time(NULL) - start > 2) {
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LOG_ERROR("Timed out waiting for debug int to clear.");
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return ERROR_FAIL;
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}
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}
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}
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static int wait_and_read(struct target *target, uint32_t *data, uint16_t address)
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{
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riscv_info_t *info = (riscv_info_t *) target->arch_info;
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@ -557,8 +600,6 @@ static int resume(struct target *target, int current, uint32_t address,
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// Write DCSR value, set interrupt and clear haltnot.
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uint64_t dbus_value = DMCONTROL_INTERRUPT | info->dcsr;
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dbus_write(target, dram_address(4), dbus_value);
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info->dram_valid |= (1<<4);
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info->dram[4] = info->dcsr;
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if (wait_for_debugint_clear(target) != ERROR_OK) {
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LOG_ERROR("Debug interrupt didn't clear.");
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@ -644,8 +685,6 @@ static int register_get(struct reg *reg)
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LOG_DEBUG("%s=0x%x", reg->name, value);
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buf_set_u32(reg->value, 0, 32, value);
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info->dram_valid &= ~1;
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return ERROR_OK;
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}
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@ -754,8 +793,6 @@ static int riscv_init_target(struct command_context *cmd_ctx,
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}
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update_reg_list(target);
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info->dram_valid = 0;
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memset(info->hwbp_unique_id, 0xff, sizeof(info->hwbp_unique_id));
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return ERROR_OK;
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@ -765,9 +802,6 @@ static void riscv_deinit_target(struct target *target)
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{
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LOG_DEBUG("riscv_deinit_target()");
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riscv_info_t *info = (riscv_info_t *) target->arch_info;
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if (info->dram) {
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free(info->dram);
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}
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free(info);
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target->arch_info = NULL;
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}
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@ -846,14 +880,6 @@ static void light_leds(struct target *target)
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}
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#endif
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static void dump_debug_ram(struct target *target)
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{
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for (unsigned int i = 0; i < 16; i++) {
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uint32_t value = dram_read32(target, i);
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LOG_ERROR("Debug RAM 0x%x: 0x%08x", i, value);
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}
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}
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#if 0
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static void write_constants(struct target *target)
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{
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@ -911,8 +937,6 @@ static int riscv_examine(struct target *target)
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info->addrbits = get_field(dtminfo, DTMINFO_ADDRBITS);
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uint32_t dminfo = dbus_read(target, DMINFO, 0);
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// TODO: need to read dminfo twice to get the correct value.
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dminfo = dbus_read(target, DMINFO, 0);
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LOG_DEBUG("dminfo: 0x%08x", dminfo);
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LOG_DEBUG(" abussize=0x%x", get_field(dminfo, DMINFO_ABUSSIZE));
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LOG_DEBUG(" serialcount=0x%x", get_field(dminfo, DMINFO_SERIALCOUNT));
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@ -928,15 +952,12 @@ static int riscv_examine(struct target *target)
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LOG_DEBUG(" version=0x%x", get_field(dminfo, DMINFO_VERSION));
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if (get_field(dminfo, DMINFO_VERSION) != 1) {
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LOG_ERROR("OpenOCD only supports Debug Module version 1, not %d",
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get_field(dminfo, DMINFO_VERSION));
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LOG_ERROR("OpenOCD only supports Debug Module version 1, not %d "
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"(dminfo=0x%x)", get_field(dminfo, DMINFO_VERSION), dminfo);
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return ERROR_FAIL;
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}
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info->dramsize = get_field(dminfo, DMINFO_DRAMSIZE) + 1;
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info->dram = malloc(info->dramsize * 4);
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if (!info->dram)
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return ERROR_FAIL;
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if (get_field(dminfo, DMINFO_AUTHTYPE) != 0) {
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LOG_ERROR("Authentication required by RISC-V core but not "
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@ -945,15 +966,20 @@ static int riscv_examine(struct target *target)
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}
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// Figure out XLEN.
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dram_write32(target, 0, xori(S1, ZERO, -1), false);
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cache_set(target, 0, xori(S1, ZERO, -1));
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// 0xffffffff 0xffffffff:ffffffff 0xffffffff:ffffffff:ffffffff:ffffffff
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dram_write32(target, 1, srli(S1, S1, 31), false);
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cache_set(target, 1, srli(S1, S1, 31));
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// 0x00000001 0x00000001:ffffffff 0x00000001:ffffffff:ffffffff:ffffffff
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dram_write32(target, 2, sw(S1, ZERO, DEBUG_RAM_START), false);
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dram_write32(target, 3, srli(S1, S1, 31), false);
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cache_set(target, 2, sw(S1, ZERO, DEBUG_RAM_START));
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cache_set(target, 3, srli(S1, S1, 31));
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// 0x00000000 0x00000000:00000003 0x00000000:00000003:ffffffff:ffffffff
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dram_write32(target, 4, sw(S1, ZERO, DEBUG_RAM_START + 4), false);
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cache_set(target, 4, sw(S1, ZERO, DEBUG_RAM_START + 4));
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cache_set_jump(target, 5);
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cache_run(target);
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#if 0
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// TODO
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// Check that we can actually read/write dram.
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int error = 0;
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error += dram_check32(target, 0, xori(S1, ZERO, -1));
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@ -965,14 +991,7 @@ static int riscv_examine(struct target *target)
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dump_debug_ram(target);
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return ERROR_FAIL;
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}
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// Execute.
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dram_write_jump(target, 5, true);
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if (wait_for_debugint_clear(target) != ERROR_OK) {
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LOG_ERROR("Debug interrupt didn't clear.");
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return ERROR_FAIL;
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}
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#endif
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uint32_t word0 = dram_read32(target, 0);
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uint32_t word1 = dram_read32(target, 1);
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@ -1235,7 +1254,6 @@ static int riscv_read_memory(struct target *target, uint32_t address,
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static int riscv_write_memory(struct target *target, uint32_t address,
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uint32_t size, uint32_t count, const uint8_t *buffer)
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{
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riscv_info_t *info = (riscv_info_t *) target->arch_info;
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jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
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// Set up the address.
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@ -1306,8 +1324,6 @@ static int riscv_write_memory(struct target *target, uint32_t address,
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LOG_ERROR("dbus write failed!");
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return ERROR_FAIL;
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}
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info->dram_valid |= (1<<4);
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info->dram[4] = value;
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}
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return register_write(target, T0, t0);
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@ -1534,6 +1550,11 @@ static int riscv_remove_breakpoint(struct target *target, struct breakpoint *bre
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return ERROR_OK;
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}
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int riscv_arch_state(struct target *target)
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{
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return ERROR_OK;
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}
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struct target_type riscv_target =
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{
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.name = "riscv",
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@ -1559,4 +1580,6 @@ struct target_type riscv_target =
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.add_breakpoint = riscv_add_breakpoint,
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.remove_breakpoint = riscv_remove_breakpoint,
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.arch_state = riscv_arch_state,
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};
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