Fix bug with slow targets.
Halting didn't work right in slow targets, because some code assumed the register cache is valid before it was guaranteed to be. Also made dbus_busy_delay and interrupt_high_delay grow faster, so that on slow targets it takes less time to learn the correct values. Change-Id: I948a49d4e3cd0638f5449ab94994406319fd5f42__archive__
parent
e6e2070692
commit
e7a745ed3b
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@ -385,7 +385,7 @@ static uint32_t idcode_scan(struct target *target)
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static void increase_dbus_busy_delay(struct target *target)
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static void increase_dbus_busy_delay(struct target *target)
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{
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{
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riscv_info_t *info = (riscv_info_t *) target->arch_info;
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riscv_info_t *info = (riscv_info_t *) target->arch_info;
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info->dbus_busy_delay++;
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info->dbus_busy_delay += info->dbus_busy_delay / 10 + 1;
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LOG_INFO("dtmcontrol_idle=%d, dbus_busy_delay=%d, interrupt_high_delay=%d",
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LOG_INFO("dtmcontrol_idle=%d, dbus_busy_delay=%d, interrupt_high_delay=%d",
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info->dtmcontrol_idle, info->dbus_busy_delay,
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info->dtmcontrol_idle, info->dbus_busy_delay,
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info->interrupt_high_delay);
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info->interrupt_high_delay);
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@ -396,7 +396,7 @@ static void increase_dbus_busy_delay(struct target *target)
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static void increase_interrupt_high_delay(struct target *target)
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static void increase_interrupt_high_delay(struct target *target)
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{
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{
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riscv_info_t *info = (riscv_info_t *) target->arch_info;
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riscv_info_t *info = (riscv_info_t *) target->arch_info;
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info->interrupt_high_delay++;
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info->interrupt_high_delay += info->interrupt_high_delay / 10 + 1;
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LOG_INFO("dtmcontrol_idle=%d, dbus_busy_delay=%d, interrupt_high_delay=%d",
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LOG_INFO("dtmcontrol_idle=%d, dbus_busy_delay=%d, interrupt_high_delay=%d",
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info->dtmcontrol_idle, info->dbus_busy_delay,
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info->dtmcontrol_idle, info->dbus_busy_delay,
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info->interrupt_high_delay);
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info->interrupt_high_delay);
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@ -1226,7 +1226,10 @@ static void update_reg_list(struct target *target)
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static uint64_t reg_cache_get(struct target *target, unsigned int number)
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static uint64_t reg_cache_get(struct target *target, unsigned int number)
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{
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{
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struct reg *r = &target->reg_cache->reg_list[number];
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struct reg *r = &target->reg_cache->reg_list[number];
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assert(r->valid);
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if (!r->valid) {
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LOG_ERROR("Register cache entry for %d is invalid!", number);
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assert(r->valid);
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}
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uint64_t value = buf_get_u64(r->value, 0, r->size);
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uint64_t value = buf_get_u64(r->value, 0, r->size);
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LOG_DEBUG("%s = 0x%" PRIx64, r->name, value);
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LOG_DEBUG("%s = 0x%" PRIx64, r->name, value);
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return value;
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return value;
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@ -1996,14 +1999,6 @@ static riscv_error_t handle_halt_routine(struct target *target)
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}
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}
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}
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}
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// TODO: get rid of those 2 variables and talk to the cache directly.
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info->dpc = reg_cache_get(target, CSR_DPC);
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info->dcsr = reg_cache_get(target, CSR_DCSR);
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scans = scans_delete(scans);
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cache_invalidate(target);
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if (dbus_busy) {
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if (dbus_busy) {
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increase_dbus_busy_delay(target);
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increase_dbus_busy_delay(target);
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return RE_AGAIN;
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return RE_AGAIN;
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@ -2013,6 +2008,14 @@ static riscv_error_t handle_halt_routine(struct target *target)
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return RE_AGAIN;
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return RE_AGAIN;
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}
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}
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// TODO: get rid of those 2 variables and talk to the cache directly.
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info->dpc = reg_cache_get(target, CSR_DPC);
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info->dcsr = reg_cache_get(target, CSR_DCSR);
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scans = scans_delete(scans);
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cache_invalidate(target);
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return RE_OK;
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return RE_OK;
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error:
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error:
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