stm32: sharpen error handling for timeouts
delete lots of crud by handling this all in one spot. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>__archive__
Øyvind Harboe
parent
fc4cbc0f98
commit
e774df7f69
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@ -54,33 +54,56 @@ FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
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return ERROR_OK;
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}
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static uint32_t stm32x_get_flash_status(struct flash_bank *bank)
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static int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
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{
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struct target *target = bank->target;
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uint32_t status;
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target_read_u32(target, STM32_FLASH_SR, &status);
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return status;
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return target_read_u32(target, STM32_FLASH_SR, status);
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}
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static uint32_t stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
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static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
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{
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struct target *target = bank->target;
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uint32_t status;
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int retval = ERROR_OK;
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/* wait for busy to clear */
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while (((status = stm32x_get_flash_status(bank)) & FLASH_BSY) && (timeout-- > 0))
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for (;;)
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{
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retval = stm32x_get_flash_status(bank, &status);
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if (retval != ERROR_OK)
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return retval;
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LOG_DEBUG("status: 0x%" PRIx32 "", status);
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if ((status & FLASH_BSY) == 0)
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break;
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if (timeout-- <= 0)
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{
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LOG_ERROR("timed out waiting for flash");
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return ERROR_FAIL;
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}
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alive_sleep(1);
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}
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if (status & FLASH_WRPRTERR)
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{
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LOG_ERROR("stm32x device protected");
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retval = ERROR_FAIL;
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}
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if (status & FLASH_PGERR)
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{
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LOG_ERROR("stm32x device programming failed");
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retval = ERROR_FAIL;
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}
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/* Clear but report errors */
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if (status & (FLASH_WRPRTERR | FLASH_PGERR))
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{
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/* If this operation fails, we ignore it and report the original
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* retval
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*/
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target_write_u32(target, STM32_FLASH_SR, FLASH_WRPRTERR | FLASH_PGERR);
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}
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return status;
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return retval;
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}
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static int stm32x_read_options(struct flash_bank *bank)
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@ -115,7 +138,6 @@ static int stm32x_erase_options(struct flash_bank *bank)
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{
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struct stm32x_flash_bank *stm32x_info = NULL;
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struct target *target = bank->target;
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uint32_t status;
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stm32x_info = bank->driver_priv;
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@ -134,12 +156,9 @@ static int stm32x_erase_options(struct flash_bank *bank)
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target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER | FLASH_OPTWRE);
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target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
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status = stm32x_wait_status_busy(bank, 10);
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if (status & FLASH_WRPRTERR)
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return ERROR_FLASH_OPERATION_FAILED;
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if (status & FLASH_PGERR)
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return ERROR_FLASH_OPERATION_FAILED;
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int retval = stm32x_wait_status_busy(bank, 10);
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if (retval != ERROR_OK)
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return retval;
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/* clear readout protection and complementary option bytes
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* this will also force a device unlock if set */
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@ -152,7 +171,6 @@ static int stm32x_write_options(struct flash_bank *bank)
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{
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struct stm32x_flash_bank *stm32x_info = NULL;
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struct target *target = bank->target;
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uint32_t status;
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stm32x_info = bank->driver_priv;
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@ -170,62 +188,44 @@ static int stm32x_write_options(struct flash_bank *bank)
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/* write user option byte */
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target_write_u16(target, STM32_OB_USER, stm32x_info->option_bytes.user_options);
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status = stm32x_wait_status_busy(bank, 10);
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if (status & FLASH_WRPRTERR)
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return ERROR_FLASH_OPERATION_FAILED;
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if (status & FLASH_PGERR)
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return ERROR_FLASH_OPERATION_FAILED;
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int retval = stm32x_wait_status_busy(bank, 10);
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if (retval != ERROR_OK)
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return retval;
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/* write protection byte 1 */
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target_write_u16(target, STM32_OB_WRP0, stm32x_info->option_bytes.protection[0]);
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status = stm32x_wait_status_busy(bank, 10);
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if (status & FLASH_WRPRTERR)
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return ERROR_FLASH_OPERATION_FAILED;
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if (status & FLASH_PGERR)
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return ERROR_FLASH_OPERATION_FAILED;
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retval = stm32x_wait_status_busy(bank, 10);
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if (retval != ERROR_OK)
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return retval;
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/* write protection byte 2 */
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target_write_u16(target, STM32_OB_WRP1, stm32x_info->option_bytes.protection[1]);
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status = stm32x_wait_status_busy(bank, 10);
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if (status & FLASH_WRPRTERR)
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return ERROR_FLASH_OPERATION_FAILED;
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if (status & FLASH_PGERR)
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return ERROR_FLASH_OPERATION_FAILED;
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retval = stm32x_wait_status_busy(bank, 10);
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if (retval != ERROR_OK)
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return retval;
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/* write protection byte 3 */
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target_write_u16(target, STM32_OB_WRP2, stm32x_info->option_bytes.protection[2]);
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status = stm32x_wait_status_busy(bank, 10);
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if (status & FLASH_WRPRTERR)
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return ERROR_FLASH_OPERATION_FAILED;
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if (status & FLASH_PGERR)
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return ERROR_FLASH_OPERATION_FAILED;
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retval = stm32x_wait_status_busy(bank, 10);
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if (retval != ERROR_OK)
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return retval;
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/* write protection byte 4 */
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target_write_u16(target, STM32_OB_WRP3, stm32x_info->option_bytes.protection[3]);
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status = stm32x_wait_status_busy(bank, 10);
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if (status & FLASH_WRPRTERR)
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return ERROR_FLASH_OPERATION_FAILED;
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if (status & FLASH_PGERR)
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return ERROR_FLASH_OPERATION_FAILED;
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retval = stm32x_wait_status_busy(bank, 10);
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if (retval != ERROR_OK)
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return retval;
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/* write readout protection bit */
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target_write_u16(target, STM32_OB_RDP, stm32x_info->option_bytes.RDP);
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status = stm32x_wait_status_busy(bank, 10);
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if (status & FLASH_WRPRTERR)
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return ERROR_FLASH_OPERATION_FAILED;
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if (status & FLASH_PGERR)
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return ERROR_FLASH_OPERATION_FAILED;
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retval = stm32x_wait_status_busy(bank, 10);
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if (retval != ERROR_OK)
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return retval;
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target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
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@ -308,7 +308,6 @@ static int stm32x_erase(struct flash_bank *bank, int first, int last)
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{
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struct target *target = bank->target;
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int i;
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uint32_t status;
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if (bank->target->state != TARGET_HALTED)
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{
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@ -331,12 +330,10 @@ static int stm32x_erase(struct flash_bank *bank, int first, int last)
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target_write_u32(target, STM32_FLASH_AR, bank->base + bank->sectors[i].offset);
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target_write_u32(target, STM32_FLASH_CR, FLASH_PER | FLASH_STRT);
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status = stm32x_wait_status_busy(bank, 100);
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int retval = stm32x_wait_status_busy(bank, 100);
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if (retval != ERROR_OK)
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return retval;
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if (status & FLASH_WRPRTERR)
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return ERROR_FLASH_OPERATION_FAILED;
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if (status & FLASH_PGERR)
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return ERROR_FLASH_OPERATION_FAILED;
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bank->sectors[i].is_erased = 1;
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}
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@ -526,7 +523,6 @@ static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
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10000, &armv7m_info)) != ERROR_OK)
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{
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LOG_ERROR("error executing stm32x flash write algorithm");
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retval = ERROR_FLASH_OPERATION_FAILED;
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break;
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}
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@ -535,7 +531,7 @@ static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
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LOG_ERROR("flash memory not erased before writing");
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/* Clear but report errors */
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target_write_u32(target, STM32_FLASH_SR, FLASH_PGERR);
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retval = ERROR_FLASH_OPERATION_FAILED;
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retval = ERROR_FAIL;
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break;
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}
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@ -544,7 +540,7 @@ static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
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LOG_ERROR("flash memory write protected");
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/* Clear but report errors */
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target_write_u32(target, STM32_FLASH_SR, FLASH_WRPRTERR);
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retval = ERROR_FLASH_OPERATION_FAILED;
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retval = ERROR_FAIL;
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break;
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}
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@ -572,7 +568,6 @@ static int stm32x_write(struct flash_bank *bank, uint8_t *buffer,
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uint32_t bytes_remaining = (count & 0x00000001);
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uint32_t address = bank->base + offset;
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uint32_t bytes_written = 0;
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uint8_t status;
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int retval;
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if (bank->target->state != TARGET_HALTED)
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@ -603,11 +598,6 @@ static int stm32x_write(struct flash_bank *bank, uint8_t *buffer,
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* we use normal (slow) single dword accesses */
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LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
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}
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else if (retval == ERROR_FLASH_OPERATION_FAILED)
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{
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LOG_ERROR("flash writing failed with error code: 0x%x", retval);
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return ERROR_FLASH_OPERATION_FAILED;
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}
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}
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else
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{
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@ -625,18 +615,9 @@ static int stm32x_write(struct flash_bank *bank, uint8_t *buffer,
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target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
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target_write_u16(target, address, value);
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status = stm32x_wait_status_busy(bank, 5);
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if (status & FLASH_WRPRTERR)
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{
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LOG_ERROR("flash memory not erased before writing");
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return ERROR_FLASH_OPERATION_FAILED;
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}
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if (status & FLASH_PGERR)
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{
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LOG_ERROR("flash memory write protected");
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return ERROR_FLASH_OPERATION_FAILED;
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}
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retval = stm32x_wait_status_busy(bank, 5);
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if (retval != ERROR_OK)
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return retval;
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bytes_written += 2;
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words_remaining--;
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@ -651,18 +632,9 @@ static int stm32x_write(struct flash_bank *bank, uint8_t *buffer,
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target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
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target_write_u16(target, address, value);
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status = stm32x_wait_status_busy(bank, 5);
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if (status & FLASH_WRPRTERR)
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{
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LOG_ERROR("flash memory not erased before writing");
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return ERROR_FLASH_OPERATION_FAILED;
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}
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if (status & FLASH_PGERR)
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{
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LOG_ERROR("flash memory write protected");
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return ERROR_FLASH_OPERATION_FAILED;
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}
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retval = stm32x_wait_status_busy(bank, 5);
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if (retval != ERROR_OK)
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return retval;
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}
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target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
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@ -770,7 +742,7 @@ static int stm32x_probe(struct flash_bank *bank)
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else
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{
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LOG_WARNING("Cannot identify target as a STM32 family.");
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return ERROR_FLASH_OPERATION_FAILED;
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return ERROR_FAIL;
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}
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LOG_INFO("flash size = %dkbytes", num_pages);
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@ -938,7 +910,7 @@ static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
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else
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{
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snprintf(buf, buf_size, "Cannot identify target as a stm32x\n");
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return ERROR_FLASH_OPERATION_FAILED;
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return ERROR_FAIL;
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}
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return ERROR_OK;
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@ -1176,7 +1148,6 @@ COMMAND_HANDLER(stm32x_handle_options_write_command)
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static int stm32x_mass_erase(struct flash_bank *bank)
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{
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struct target *target = bank->target;
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uint32_t status;
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if (target->state != TARGET_HALTED)
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{
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@ -1192,22 +1163,12 @@ static int stm32x_mass_erase(struct flash_bank *bank)
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target_write_u32(target, STM32_FLASH_CR, FLASH_MER);
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target_write_u32(target, STM32_FLASH_CR, FLASH_MER | FLASH_STRT);
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status = stm32x_wait_status_busy(bank, 100);
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int retval = stm32x_wait_status_busy(bank, 100);
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if (retval != ERROR_OK)
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return retval;
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target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
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if (status & FLASH_WRPRTERR)
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{
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LOG_ERROR("stm32x device protected");
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return ERROR_FLASH_OPERATION_FAILED;
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}
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if (status & FLASH_PGERR)
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{
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LOG_ERROR("stm32x device programming failed");
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return ERROR_FLASH_OPERATION_FAILED;
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}
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return ERROR_OK;
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}
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