From e430dbd89465d23dc8ad224f396c890994584958 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Andreas=20F=C3=A4rber?= <afaerber@suse.de>
Date: Thu, 14 May 2015 22:02:00 +0200
Subject: [PATCH] tcl/target: Add Freescale Vybrid VF6xx config
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This covers only the Cortex-A5 for now, not the Cortex-M4.

Change-Id: I739ec52b14b83d6e9f124ed61f8941502e481402
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/2766
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
---
 tcl/target/vybrid_vf6xx.cfg | 36 ++++++++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)
 create mode 100644 tcl/target/vybrid_vf6xx.cfg

diff --git a/tcl/target/vybrid_vf6xx.cfg b/tcl/target/vybrid_vf6xx.cfg
new file mode 100644
index 000000000..6ec4b35cd
--- /dev/null
+++ b/tcl/target/vybrid_vf6xx.cfg
@@ -0,0 +1,36 @@
+#
+# Freescale Vybrid VF610
+#
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME vf610
+}
+
+if { [info exists A5_JTAG_TAPID] } {
+	set _A5_JTAG_TAPID $A5_JTAG_TAPID
+} else {
+	set _A5_JTAG_TAPID 0x4BA00477
+}
+
+if { [info exists A5_SWD_TAPID] } {
+	set _A5_SWD_TAPID $A5_SWD_TAPID
+} else {
+	set _A5_SWD_TAPID 0x3BA02477
+}
+
+if { [using_jtag] } {
+	set _A5_TAPID $_A5_JTAG_TAPID
+} else {
+	set _A5_TAPID $_A5_SWD_TAPID
+}
+
+source [find target/swj-dp.tcl]
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_A5_TAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create ${_TARGETNAME}0 cortex_a -chain-position $_CHIPNAME.cpu -dbgbase 0xc0088000
+
+adapter_khz 1000