optional crc for flash writing

crc check was always performed on newly flashed data, now it is optional
flash mem can be locked by writing a specific word to a specific address in flash.
to verify flash, target must be halted, and this will (when the new halt sequence is implemented) require reseting the chip. if the target is reset after writing the lock words, then it will lock, hence the CRC will fail because it is not possible to read stuff from the target.

also added a function that resets the jtag state machine.
this is not used yet, but will be soon.
it is implemented to allow strict control over JTAG state machine, necessary to implement to halt and unlocking sequences.

src/flash/nor/dsp5680xx_flash.c

@@ -157,7 +157,7 @@ static int dsp5680xx_flash_write(struct flash_bank *bank, uint8_t *buffer, uint3
     LOG_ERROR("%s: Writing to odd addresses not supported. This chip uses word addressing, Openocd only supports byte addressing. The workaround results in disabling writing to odd byte addresses.",__FUNCTION__);
     return ERROR_FAIL;
   }
-  retval = dsp5680xx_f_wr(bank->target,  buffer, bank->base + offset/2,  count);
+  retval = dsp5680xx_f_wr(bank->target,  buffer, bank->base + offset/2,  count, 0);
   uint32_t addr_word;
   for(addr_word = bank->base + offset/2;addr_word<count/2;addr_word+=(HFM_SECTOR_SIZE/2)){
     if(retval == ERROR_OK)

src/target/dsp5680xx.c

@@ -1341,7 +1341,7 @@ int dsp5680xx_f_erase(struct target * target, int first, int last){
 const uint16_t pgm_write_pflash[] = {0x8A46,0x0013,0x407D,0xE700,0xE700,0x8A44,0xFFFE,0x017B,0xE700,0xF514,0x8563,0x8646,0x0020,0x0014,0x8646,0x0080,0x0013,0x8A46,0x0013,0x2004,0x8246,0x0013,0x0020,0xA968,0x8A46,0x0013,0x1065,0x8246,0x0013,0x0010,0xA961};
 const uint32_t pgm_write_pflash_length = 31;
 
-int dsp5680xx_f_wr(struct target * target, uint8_t *buffer, uint32_t address, uint32_t count){
+int dsp5680xx_f_wr(struct target * target, uint8_t *buffer, uint32_t address, uint32_t count, int is_flash_lock){
   int retval = ERROR_OK;
   if (dsp5680xx_target_status(target,NULL,NULL) != TARGET_HALTED){
     retval = eonce_enter_debug_mode(target,NULL);
@@ -1351,10 +1351,12 @@ int dsp5680xx_f_wr(struct target * target, uint8_t *buffer, uint32_t address, ui
   // Download the pgm that flashes.
   // -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
   uint32_t my_favourite_ram_address = 0x8700; // This seems to be a safe address. This one is the one used by codewarrior in 56801x_flash.cfg
-  retval = dsp5680xx_write(target, my_favourite_ram_address, 1, pgm_write_pflash_length*2,(uint8_t *) pgm_write_pflash);
-  err_check_propagate(retval);
-  retval = dsp5680xx_execute_queue();
-  err_check_propagate(retval);
+  if(!is_flash_lock){
+    retval = dsp5680xx_write(target, my_favourite_ram_address, 1, pgm_write_pflash_length*2,(uint8_t *) pgm_write_pflash);
+    err_check_propagate(retval);
+    retval = dsp5680xx_execute_queue();
+    err_check_propagate(retval);
+  }
   // -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
   // Set hfmdiv
   // -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
@@ -1422,21 +1424,38 @@ int dsp5680xx_f_wr(struct target * target, uint8_t *buffer, uint32_t address, ui
 	dsp5680xx_context.flush = 0;
   }
   dsp5680xx_context.flush = 1;
-  // -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-  // Verify flash
-  // -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-  uint16_t signature;
-  uint16_t pc_crc;
-  retval =  dsp5680xx_f_signature(target,address,i,&signature);
-  err_check_propagate(retval);
-  pc_crc = perl_crc(buffer,i);
-  if(pc_crc != signature){
-    retval = ERROR_FAIL;
-    err_check(retval,"Flashed data failed CRC check, flash again!");
+  if(!is_flash_lock){
+    // -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
+    // Verify flash (skip when exec lock sequence)
+    // -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
+    uint16_t signature;
+    uint16_t pc_crc;
+    retval =  dsp5680xx_f_signature(target,address,i,&signature);
+    err_check_propagate(retval);
+    pc_crc = perl_crc(buffer,i);
+    if(pc_crc != signature){
+      retval = ERROR_FAIL;
+      err_check(retval,"Flashed data failed CRC check, flash again!");
+    }
   }
   return retval;
 }
 
+// Reset state machine
+int reset_jtag(void){
+  int retval;
+  tap_state_t states[2];
+  const char *cp = "RESET";
+  states[0] = tap_state_by_name(cp);
+  retval = jtag_add_statemove(states[0]);
+  err_check_propagate(retval);
+  retval = jtag_execute_queue();
+  err_check_propagate(retval);
+  jtag_add_pathmove(0, states + 1);
+  retval = jtag_execute_queue();
+  return retval;
+}
+
 int dsp5680xx_f_unlock(struct target * target){
   int retval;
   if(target->tap->enabled){
@@ -1457,7 +1476,7 @@ int dsp5680xx_f_unlock(struct target * target){
 int dsp5680xx_f_lock(struct target * target){
   int retval;
   uint16_t lock_word[] = {HFM_LOCK_FLASH,HFM_LOCK_FLASH};
-  retval = dsp5680xx_f_wr(target,(uint8_t *)(lock_word),HFM_LOCK_ADDR_L,4);
+  retval = dsp5680xx_f_wr(target,(uint8_t *)(lock_word),HFM_LOCK_ADDR_L,4,1);
   err_check_propagate(retval);
   return retval;
 }

src/target/dsp5680xx.h

@@ -234,10 +234,11 @@ static inline struct dsp5680xx_common *target_to_dsp5680xx(struct target *target
  * @param buffer 
  * @param address Word addressing.
  * @param count In bytes. 
+ * @param verify_flash Execute a CRC check after flashing. 
  * 
  * @return 
  */
-int dsp5680xx_f_wr(struct target * target, uint8_t *buffer, uint32_t address, uint32_t count);
+int dsp5680xx_f_wr(struct target * target, uint8_t *buffer, uint32_t address, uint32_t count, int is_flash_lock);
 
 /** 
  * The FM has the funcionality of checking if the flash array is erased. This function executes it. It does not support individual sector analysis.