Cortex-A8: hook up DPM
This replaces two versions of register access functions. One was commented out, and seemed to have uncertain intent. The other was fairly new, and helped motivate the DPM framework once I observed that the ARM11 was doing the very same ops. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>__archive__
David Brownell
parent
c008d30fe8
commit
e109bb6af2
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@ -496,8 +496,7 @@ static int cortex_a8_instr_read_data_r0(struct arm_dpm *dpm,
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return cortex_a8_read_dcc(a8, data);
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}
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// static
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int cortex_a8_dpm_setup(struct cortex_a8_common *a8, uint32_t didr)
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static int cortex_a8_dpm_setup(struct cortex_a8_common *a8, uint32_t didr)
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{
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struct arm_dpm *dpm = &a8->armv7a_common.dpm;
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@ -806,12 +805,7 @@ static int cortex_a8_debug_entry(struct target *target)
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/* First load register acessible through core debug port*/
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if (!regfile_working_area)
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{
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/* FIXME we don't actually need all these registers;
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* reading them slows us down. Just R0, PC, CPSR...
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*/
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for (i = 0; i <= 15; i++)
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cortex_a8_dap_read_coreregister_u32(target,
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®file[i], i);
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retval = arm_dpm_read_current_registers(&armv7a->dpm);
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}
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else
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{
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@ -820,7 +814,6 @@ static int cortex_a8_debug_entry(struct target *target)
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regfile_working_area->address, regfile);
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dap_ap_select(swjdp, swjdp_memoryap);
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target_free_working_area(target, regfile_working_area);
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}
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/* read Current PSR */
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cortex_a8_dap_read_coreregister_u32(target, &cpsr, 16);
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@ -855,9 +848,7 @@ static int cortex_a8_debug_entry(struct target *target)
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reg = armv4_5->core_cache->reg_list + 15;
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buf_set_u32(reg->value, 0, 32, regfile[ARM_PC]);
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reg->dirty = reg->valid;
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ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15)
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.dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
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armv4_5->core_mode, 15).valid;
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}
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#if 0
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/* TODO, Move this */
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@ -992,83 +983,14 @@ static int cortex_a8_step(struct target *target, int current, uint32_t address,
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static int cortex_a8_restore_context(struct target *target)
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{
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uint32_t value;
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struct armv7a_common *armv7a = target_to_armv7a(target);
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struct reg_cache *cache = armv7a->armv4_5_common.core_cache;
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unsigned max = cache->num_regs;
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struct reg *r;
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bool flushed, flush_cpsr = false;
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LOG_DEBUG(" ");
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if (armv7a->pre_restore_context)
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armv7a->pre_restore_context(target);
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/* Flush all dirty registers from the cache, one mode at a time so
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* that we write CPSR as little as possible. Save CPSR and R0 for
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* last; they're used to change modes and write other registers.
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*
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* REVISIT be smarter: save eventual mode for last loop, don't
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* need to write CPSR an extra time.
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*/
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do {
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enum armv4_5_mode mode = ARMV4_5_MODE_ANY;
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unsigned i;
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flushed = false;
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/* write dirty non-{R0,CPSR} registers sharing the same mode */
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for (i = max - 1, r = cache->reg_list + 1; i > 0; i--, r++) {
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struct arm_reg *reg;
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if (!r->dirty || r == armv7a->armv4_5_common.cpsr)
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continue;
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reg = r->arch_info;
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/* TODO Check return values */
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/* Pick a mode and update CPSR; else ignore this
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* register if it's for a different mode than what
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* we're handling on this pass.
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*
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* REVISIT don't distinguish SYS and USR modes.
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*
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* FIXME if we restore from FIQ mode, R8..R12 will
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* get wrongly flushed onto FIQ shadows...
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*/
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if (mode == ARMV4_5_MODE_ANY) {
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mode = reg->mode;
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if (mode != ARMV4_5_MODE_ANY) {
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cortex_a8_dap_write_coreregister_u32(
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target, mode, 16);
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flush_cpsr = true;
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}
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} else if (mode != reg->mode)
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continue;
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/* Write this register */
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value = buf_get_u32(r->value, 0, 32);
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cortex_a8_dap_write_coreregister_u32(target, value,
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(reg->num == 16) ? 17 : reg->num);
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r->dirty = false;
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flushed = true;
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}
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} while (flushed);
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/* now flush CPSR if needed ... */
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r = armv7a->armv4_5_common.cpsr;
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if (flush_cpsr || r->dirty) {
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value = buf_get_u32(r->value, 0, 32);
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cortex_a8_dap_write_coreregister_u32(target, value, 16);
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r->dirty = false;
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}
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/* ... and R0 always (it was dirtied when we saved context) */
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r = cache->reg_list + 0;
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value = buf_get_u32(r->value, 0, 32);
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cortex_a8_dap_write_coreregister_u32(target, value, 0);
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r->dirty = false;
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arm_dpm_write_dirty_registers(&armv7a->dpm);
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if (armv7a->post_restore_context)
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armv7a->post_restore_context(target);
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@ -1077,204 +999,6 @@ static int cortex_a8_restore_context(struct target *target)
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}
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#if 0
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/*
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* Cortex-A8 Core register functions
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*/
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static int cortex_a8_load_core_reg_u32(struct target *target, int num,
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armv4_5_mode_t mode, uint32_t * value)
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{
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int retval;
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struct arm *armv4_5 = target_to_armv4_5(target);
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if ((num <= ARM_CPSR))
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{
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/* read a normal core register */
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retval = cortex_a8_dap_read_coreregister_u32(target, value, num);
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if (retval != ERROR_OK)
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{
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LOG_ERROR("JTAG failure %i", retval);
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return ERROR_JTAG_DEVICE_ERROR;
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}
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LOG_DEBUG("load from core reg %i value 0x%" PRIx32, num, *value);
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}
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else
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{
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return ERROR_INVALID_ARGUMENTS;
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}
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/* Register other than r0 - r14 uses r0 for access */
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if (num > 14)
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ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
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armv4_5->core_mode, 0).dirty =
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ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
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armv4_5->core_mode, 0).valid;
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ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
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armv4_5->core_mode, 15).dirty =
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ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
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armv4_5->core_mode, 15).valid;
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return ERROR_OK;
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}
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static int cortex_a8_store_core_reg_u32(struct target *target, int num,
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armv4_5_mode_t mode, uint32_t value)
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{
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int retval;
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// uint32_t reg;
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struct arm *armv4_5 = target_to_armv4_5(target);
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#ifdef ARMV7_GDB_HACKS
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/* If the LR register is being modified, make sure it will put us
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* in "thumb" mode, or an INVSTATE exception will occur. This is a
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* hack to deal with the fact that gdb will sometimes "forge"
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* return addresses, and doesn't set the LSB correctly (i.e., when
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* printing expressions containing function calls, it sets LR=0.) */
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if (num == 14)
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value |= 0x01;
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#endif
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if ((num <= ARM_CPSR))
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{
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retval = cortex_a8_dap_write_coreregister_u32(target, value, num);
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if (retval != ERROR_OK)
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{
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LOG_ERROR("JTAG failure %i", retval);
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ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
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armv4_5->core_mode, num).dirty =
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ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
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armv4_5->core_mode, num).valid;
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return ERROR_JTAG_DEVICE_ERROR;
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}
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LOG_DEBUG("write core reg %i value 0x%" PRIx32, num, value);
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}
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else
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{
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return ERROR_INVALID_ARGUMENTS;
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}
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return ERROR_OK;
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}
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#endif
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static int cortex_a8_write_core_reg(struct target *target, struct reg *r,
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int num, enum armv4_5_mode mode, uint32_t value);
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static int cortex_a8_read_core_reg(struct target *target, struct reg *r,
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int num, enum armv4_5_mode mode)
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{
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uint32_t value;
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int retval;
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struct arm *armv4_5 = target_to_armv4_5(target);
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struct reg *cpsr_r = NULL;
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uint32_t cpsr = 0;
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unsigned cookie = num;
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/* avoid some needless mode changes
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* FIXME move some of these to shared ARM code...
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*/
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if (mode != armv4_5->core_mode) {
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if ((armv4_5->core_mode == ARMV4_5_MODE_SYS)
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&& (mode == ARMV4_5_MODE_USR))
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mode = ARMV4_5_MODE_ANY;
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else if ((mode != ARMV4_5_MODE_FIQ) && (num <= 12))
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mode = ARMV4_5_MODE_ANY;
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if (mode != ARMV4_5_MODE_ANY) {
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cpsr_r = armv4_5->cpsr;
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cpsr = buf_get_u32(cpsr_r->value, 0, 32);
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cortex_a8_write_core_reg(target, cpsr_r,
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16, ARMV4_5_MODE_ANY, mode);
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}
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}
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if (num == 16) {
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switch (mode) {
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case ARMV4_5_MODE_USR:
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case ARMV4_5_MODE_SYS:
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case ARMV4_5_MODE_ANY:
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/* CPSR */
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break;
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default:
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/* SPSR */
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cookie++;
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break;
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}
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}
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cortex_a8_dap_read_coreregister_u32(target, &value, cookie);
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retval = jtag_execute_queue();
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if (retval == ERROR_OK) {
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r->valid = 1;
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r->dirty = 0;
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buf_set_u32(r->value, 0, 32, value);
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}
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if (cpsr_r)
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cortex_a8_write_core_reg(target, cpsr_r,
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16, ARMV4_5_MODE_ANY, cpsr);
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return retval;
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}
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static int cortex_a8_write_core_reg(struct target *target, struct reg *r,
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int num, enum armv4_5_mode mode, uint32_t value)
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{
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int retval;
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struct arm *armv4_5 = target_to_armv4_5(target);
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struct reg *cpsr_r = NULL;
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uint32_t cpsr = 0;
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unsigned cookie = num;
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/* avoid some needless mode changes
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* FIXME move some of these to shared ARM code...
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*/
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if (mode != armv4_5->core_mode) {
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if ((armv4_5->core_mode == ARMV4_5_MODE_SYS)
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&& (mode == ARMV4_5_MODE_USR))
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mode = ARMV4_5_MODE_ANY;
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else if ((mode != ARMV4_5_MODE_FIQ) && (num <= 12))
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mode = ARMV4_5_MODE_ANY;
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if (mode != ARMV4_5_MODE_ANY) {
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cpsr_r = armv4_5->cpsr;
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cpsr = buf_get_u32(cpsr_r->value, 0, 32);
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cortex_a8_write_core_reg(target, cpsr_r,
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16, ARMV4_5_MODE_ANY, mode);
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}
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}
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if (num == 16) {
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switch (mode) {
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case ARMV4_5_MODE_USR:
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case ARMV4_5_MODE_SYS:
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case ARMV4_5_MODE_ANY:
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/* CPSR */
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break;
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default:
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/* SPSR */
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cookie++;
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break;
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}
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}
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cortex_a8_dap_write_coreregister_u32(target, value, cookie);
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if ((retval = jtag_execute_queue()) == ERROR_OK) {
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buf_set_u32(r->value, 0, 32, value);
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r->valid = 1;
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r->dirty = 0;
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}
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if (cpsr_r)
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cortex_a8_write_core_reg(target, cpsr_r,
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16, ARMV4_5_MODE_ANY, cpsr);
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return retval;
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}
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/*
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* Cortex-A8 Breakpoint and watchpoint fuctions
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*/
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@ -1696,6 +1420,8 @@ static int cortex_a8_examine_first(struct target *target)
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LOG_DEBUG("ttypr = 0x%08" PRIx32, ttypr);
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LOG_DEBUG("didr = 0x%08" PRIx32, didr);
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cortex_a8_dpm_setup(cortex_a8, didr);
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/* Setup Breakpoint Register Pairs */
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cortex_a8->brp_num = ((didr >> 24) & 0x0F) + 1;
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cortex_a8->brp_num_context = ((didr >> 20) & 0x0F) + 1;
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@ -1752,21 +1478,10 @@ static int cortex_a8_examine(struct target *target)
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* Cortex-A8 target creation and initialization
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*/
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static void cortex_a8_build_reg_cache(struct target *target)
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{
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struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
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struct arm *armv4_5 = target_to_armv4_5(target);
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armv4_5->core_type = ARM_MODE_MON;
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(*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
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}
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static int cortex_a8_init_target(struct command_context *cmd_ctx,
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struct target *target)
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{
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cortex_a8_build_reg_cache(target);
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/* examine_first() does a bunch of this */
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return ERROR_OK;
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}
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@ -1818,9 +1533,6 @@ static int cortex_a8_init_arch_info(struct target *target,
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// arm7_9->handle_target_request = cortex_a8_handle_target_request;
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armv4_5->read_core_reg = cortex_a8_read_core_reg;
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armv4_5->write_core_reg = cortex_a8_write_core_reg;
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/* REVISIT v7a setup should be in a v7a-specific routine */
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armv4_5_init_arch_info(target, armv4_5);
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armv7a->common_magic = ARMV7_COMMON_MAGIC;
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