aarch64: report the correct reason for halting after singlestep
Don't report breakpoint as debug reason when halt is due to a single-step event. Change-Id: Ie6c3ca1e5427c73eb726a038301b6a29a47d1217 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>gitignore-build
parent
11bc04e00c
commit
df7069af55
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@ -1246,7 +1246,7 @@ static int aarch64_step(struct target *target, int current, target_addr_t addres
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{
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struct armv8_common *armv8 = target_to_armv8(target);
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int retval;
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uint32_t tmp;
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uint32_t edecr;
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if (target->state != TARGET_HALTED) {
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LOG_WARNING("target not halted");
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@ -1254,25 +1254,26 @@ static int aarch64_step(struct target *target, int current, target_addr_t addres
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}
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retval = mem_ap_read_atomic_u32(armv8->debug_ap,
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armv8->debug_base + CPUV8_DBG_EDECR, &tmp);
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armv8->debug_base + CPUV8_DBG_EDECR, &edecr);
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if (retval != ERROR_OK)
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return retval;
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/* make sure EDECR.SS is not set when restoring the register */
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edecr &= ~0x4;
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/* set EDECR.SS to enter hardware step mode */
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retval = mem_ap_write_atomic_u32(armv8->debug_ap,
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armv8->debug_base + CPUV8_DBG_EDECR, (tmp|0x4));
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armv8->debug_base + CPUV8_DBG_EDECR, (edecr|0x4));
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if (retval != ERROR_OK)
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return retval;
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target->debug_reason = DBG_REASON_SINGLESTEP;
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/* resume the target */
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retval = aarch64_resume(target, current, address, 0, 0);
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if (retval != ERROR_OK)
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return retval;
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long long then = timeval_ms();
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while (target->state != TARGET_HALTED) {
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mem_ap_read_atomic_u32(armv8->debug_ap,
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armv8->debug_base + CPUV8_DBG_EDESR, &tmp);
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LOG_DEBUG("DESR = %#x", tmp);
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retval = aarch64_poll(target);
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if (retval != ERROR_OK)
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return retval;
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@ -1282,15 +1283,12 @@ static int aarch64_step(struct target *target, int current, target_addr_t addres
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}
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}
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/* restore EDECR */
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retval = mem_ap_write_atomic_u32(armv8->debug_ap,
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armv8->debug_base + CPUV8_DBG_EDECR, (tmp&(~0x4)));
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armv8->debug_base + CPUV8_DBG_EDECR, edecr);
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if (retval != ERROR_OK)
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return retval;
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target_call_event_callbacks(target, TARGET_EVENT_HALTED);
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if (target->state == TARGET_HALTED)
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LOG_DEBUG("target stepped");
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return ERROR_OK;
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}
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@ -874,11 +874,14 @@ void armv8_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dscr)
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target->debug_reason = DBG_REASON_DBGRQ;
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break;
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case DSCRV8_ENTRY_HALT_STEP_EXECLU: /* HALT step */
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case DSCRV8_ENTRY_HALT_STEP_NORMAL: /* Halt step*/
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case DSCRV8_ENTRY_HALT_STEP:
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target->debug_reason = DBG_REASON_SINGLESTEP;
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break;
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case DSCRV8_ENTRY_BKPT: /* SW BKPT */
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case DSCRV8_ENTRY_RESET_CATCH: /* Reset catch */
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case DSCRV8_ENTRY_OS_UNLOCK: /*OS unlock catch*/
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case DSCRV8_ENTRY_EXCEPTION_CATCH: /*exception catch*/
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case DSCRV8_ENTRY_HALT_STEP_NORMAL: /* Halt step*/
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case DSCRV8_ENTRY_SW_ACCESS_DBG: /*SW access dbg register*/
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target->debug_reason = DBG_REASON_BREAKPOINT;
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break;
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