cortex-a8: more MMU support
+ virt2phys() can now convert virtual address to real + read_memory() and write_memory() are renamed to read_phys_memory() and write_phys_memory() + new read_memory() and write_memory() try to resolve real address if mmu is enambled than perform real address reading/writing + if address is bellow 0xc000000 than TTB0 is used for page table dereference, if above - than TTB1. Linux style of user/kernel address separation + if above fails (i.e address is unspecified) than mode is checked whether it is Supervisor (than TTB1) or User (than TTB0) - Software breakpoints doesn't work. You should invoke "gdb_breakpoint_override hard" before you start debugging + cortex_a8_mmu(), cortex_a8_enable_mmu_caches(), cortex_a8_disable_mmu_caches() are implemented Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>__archive__
Anton Fedotov
Øyvind Harboe
parent
a8a9eddca0
commit
decad30865
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@ -51,6 +51,16 @@ static int cortex_a8_dap_read_coreregister_u32(struct target *target,
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uint32_t *value, int regnum);
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static int cortex_a8_dap_write_coreregister_u32(struct target *target,
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uint32_t value, int regnum);
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static int cortex_a8_mmu(struct target *target, int *enabled);
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static int cortex_a8_virt2phys(struct target *target,
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uint32_t virt, uint32_t *phys);
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static void cortex_a8_disable_mmu_caches(struct target *target, int mmu,
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int d_u_cache, int i_cache);
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static void cortex_a8_enable_mmu_caches(struct target *target, int mmu,
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int d_u_cache, int i_cache);
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static uint32_t cortex_a8_get_ttb(struct target *target);
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/*
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* FIXME do topology discovery using the ROM; don't
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* assume this is an OMAP3. Also, allow for multiple ARMv7-A
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@ -1269,111 +1279,158 @@ static int cortex_a8_deassert_reset(struct target *target)
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* ap number for every access.
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*/
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static int cortex_a8_read_phys_memory(struct target *target,
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uint32_t address, uint32_t size,
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uint32_t count, uint8_t *buffer)
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{
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struct armv7a_common *armv7a = target_to_armv7a(target);
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struct adiv5_dap *swjdp = &armv7a->dap;
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int retval = ERROR_INVALID_ARGUMENTS;
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/* cortex_a8 handles unaligned memory access */
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// ??? dap_ap_select(swjdp, swjdp_memoryap);
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LOG_DEBUG("Reading memory at real address 0x%x; size %d; count %d", address, size, count);
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if (count && buffer) {
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switch (size) {
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case 4:
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retval = mem_ap_read_buf_u32(swjdp, buffer, 4 * count, address);
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break;
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case 2:
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retval = mem_ap_read_buf_u16(swjdp, buffer, 2 * count, address);
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break;
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case 1:
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retval = mem_ap_read_buf_u8(swjdp, buffer, count, address);
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break;
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}
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}
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return retval;
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}
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static int cortex_a8_read_memory(struct target *target, uint32_t address,
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uint32_t size, uint32_t count, uint8_t *buffer)
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{
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struct armv7a_common *armv7a = target_to_armv7a(target);
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struct adiv5_dap *swjdp = &armv7a->dap;
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int retval = ERROR_INVALID_ARGUMENTS;
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int enabled = 0;
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uint32_t virt, phys;
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/* cortex_a8 handles unaligned memory access */
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// ??? dap_ap_select(swjdp, swjdp_memoryap);
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LOG_DEBUG("Reading memory at address 0x%x; size %d; count %d", address, size, count);
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cortex_a8_mmu(target, &enabled);
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if(enabled)
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{
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virt = address;
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cortex_a8_virt2phys(target, virt, &phys);
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LOG_DEBUG("Reading at virtual address. Translating v:0x%x to r:0x%x", virt, phys);
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address = phys;
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}
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if (count && buffer) {
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switch (size) {
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case 4:
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retval = mem_ap_read_buf_u32(swjdp, buffer, 4 * count, address);
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break;
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case 2:
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retval = mem_ap_read_buf_u16(swjdp, buffer, 2 * count, address);
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break;
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case 1:
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retval = mem_ap_read_buf_u8(swjdp, buffer, count, address);
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break;
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}
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}
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return cortex_a8_read_phys_memory(target, address, size, count, buffer);
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}
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return retval;
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static int cortex_a8_write_phys_memory(struct target *target,
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uint32_t address, uint32_t size,
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uint32_t count, uint8_t *buffer)
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{
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struct armv7a_common *armv7a = target_to_armv7a(target);
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struct adiv5_dap *swjdp = &armv7a->dap;
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int retval = ERROR_INVALID_ARGUMENTS;
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// ??? dap_ap_select(swjdp, swjdp_memoryap);
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LOG_DEBUG("Writing memory to real address 0x%x; size %d; count %d", address, size, count);
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if (count && buffer) {
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switch (size) {
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case 4:
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retval = mem_ap_write_buf_u32(swjdp, buffer, 4 * count, address);
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break;
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case 2:
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retval = mem_ap_write_buf_u16(swjdp, buffer, 2 * count, address);
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break;
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case 1:
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retval = mem_ap_write_buf_u8(swjdp, buffer, count, address);
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break;
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}
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}
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/* REVISIT this op is generic ARMv7-A/R stuff */
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if (retval == ERROR_OK && target->state == TARGET_HALTED)
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{
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struct arm_dpm *dpm = armv7a->armv4_5_common.dpm;
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retval = dpm->prepare(dpm);
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if (retval != ERROR_OK)
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return retval;
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/* The Cache handling will NOT work with MMU active, the
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* wrong addresses will be invalidated!
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*
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* For both ICache and DCache, walk all cache lines in the
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* address range. Cortex-A8 has fixed 64 byte line length.
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*
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* REVISIT per ARMv7, these may trigger watchpoints ...
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*/
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/* invalidate I-Cache */
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if (armv7a->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
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{
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/* ICIMVAU - Invalidate Cache single entry
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* with MVA to PoU
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* MCR p15, 0, r0, c7, c5, 1
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*/
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for (uint32_t cacheline = address;
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cacheline < address + size * count;
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cacheline += 64) {
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retval = dpm->instr_write_data_r0(dpm,
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ARMV4_5_MCR(15, 0, 0, 7, 5, 1),
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cacheline);
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}
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}
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/* invalidate D-Cache */
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if (armv7a->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
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{
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/* DCIMVAC - Invalidate data Cache line
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* with MVA to PoC
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* MCR p15, 0, r0, c7, c6, 1
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*/
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for (uint32_t cacheline = address;
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cacheline < address + size * count;
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cacheline += 64) {
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retval = dpm->instr_write_data_r0(dpm,
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ARMV4_5_MCR(15, 0, 0, 7, 6, 1),
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cacheline);
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}
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}
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/* (void) */ dpm->finish(dpm);
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}
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return retval;
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}
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static int cortex_a8_write_memory(struct target *target, uint32_t address,
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uint32_t size, uint32_t count, uint8_t *buffer)
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uint32_t size, uint32_t count, uint8_t *buffer)
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{
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struct armv7a_common *armv7a = target_to_armv7a(target);
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struct adiv5_dap *swjdp = &armv7a->dap;
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int retval = ERROR_INVALID_ARGUMENTS;
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int enabled = 0;
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uint32_t virt, phys;
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// ??? dap_ap_select(swjdp, swjdp_memoryap);
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// ??? dap_ap_select(swjdp, swjdp_memoryap);
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if (count && buffer) {
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switch (size) {
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case 4:
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retval = mem_ap_write_buf_u32(swjdp, buffer, 4 * count, address);
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break;
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case 2:
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retval = mem_ap_write_buf_u16(swjdp, buffer, 2 * count, address);
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break;
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case 1:
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retval = mem_ap_write_buf_u8(swjdp, buffer, count, address);
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break;
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}
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}
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LOG_DEBUG("Writing memory to address 0x%x; size %d; count %d", address, size, count);
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cortex_a8_mmu(target, &enabled);
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if(enabled)
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{
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virt = address;
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cortex_a8_virt2phys(target, virt, &phys);
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LOG_DEBUG("Writing to virtual address. Translating v:0x%x to r:0x%x", virt, phys);
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address = phys;
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}
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/* REVISIT this op is generic ARMv7-A/R stuff */
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if (retval == ERROR_OK && target->state == TARGET_HALTED)
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{
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struct arm_dpm *dpm = armv7a->armv4_5_common.dpm;
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retval = dpm->prepare(dpm);
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if (retval != ERROR_OK)
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return retval;
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/* The Cache handling will NOT work with MMU active, the
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* wrong addresses will be invalidated!
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*
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* For both ICache and DCache, walk all cache lines in the
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* address range. Cortex-A8 has fixed 64 byte line length.
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*
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* REVISIT per ARMv7, these may trigger watchpoints ...
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*/
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/* invalidate I-Cache */
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if (armv7a->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
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{
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/* ICIMVAU - Invalidate Cache single entry
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* with MVA to PoU
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* MCR p15, 0, r0, c7, c5, 1
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*/
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for (uint32_t cacheline = address;
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cacheline < address + size * count;
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cacheline += 64) {
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retval = dpm->instr_write_data_r0(dpm,
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ARMV4_5_MCR(15, 0, 0, 7, 5, 1),
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cacheline);
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}
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}
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/* invalidate D-Cache */
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if (armv7a->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
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{
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/* DCIMVAC - Invalidate data Cache line
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* with MVA to PoC
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* MCR p15, 0, r0, c7, c6, 1
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*/
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for (uint32_t cacheline = address;
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cacheline < address + size * count;
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cacheline += 64) {
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retval = dpm->instr_write_data_r0(dpm,
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ARMV4_5_MCR(15, 0, 0, 7, 6, 1),
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cacheline);
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}
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}
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/* (void) */ dpm->finish(dpm);
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}
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return retval;
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return cortex_a8_write_phys_memory(target, address, size,
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count, buffer);
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}
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static int cortex_a8_bulk_write_memory(struct target *target, uint32_t address,
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@ -1580,6 +1637,9 @@ static int cortex_a8_init_arch_info(struct target *target,
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cortex_a8->fast_reg_read = 0;
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/* Set default value */
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cortex_a8->current_address_mode = ARM_MODE_ANY;
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/* register arch-specific functions */
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armv7a->examine_debug_reason = NULL;
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@ -1587,11 +1647,11 @@ static int cortex_a8_init_arch_info(struct target *target,
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armv7a->pre_restore_context = NULL;
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armv7a->armv4_5_mmu.armv4_5_cache.ctype = -1;
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// armv7a->armv4_5_mmu.get_ttb = armv7a_get_ttb;
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armv7a->armv4_5_mmu.read_memory = cortex_a8_read_memory;
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armv7a->armv4_5_mmu.write_memory = cortex_a8_write_memory;
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// armv7a->armv4_5_mmu.disable_mmu_caches = armv7a_disable_mmu_caches;
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// armv7a->armv4_5_mmu.enable_mmu_caches = armv7a_enable_mmu_caches;
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armv7a->armv4_5_mmu.get_ttb = cortex_a8_get_ttb;
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armv7a->armv4_5_mmu.read_memory = cortex_a8_read_phys_memory;
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armv7a->armv4_5_mmu.write_memory = cortex_a8_write_phys_memory;
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armv7a->armv4_5_mmu.disable_mmu_caches = cortex_a8_disable_mmu_caches;
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armv7a->armv4_5_mmu.enable_mmu_caches = cortex_a8_enable_mmu_caches;
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armv7a->armv4_5_mmu.has_tiny_pages = 1;
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armv7a->armv4_5_mmu.mmu_enabled = 0;
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@ -1616,6 +1676,160 @@ static int cortex_a8_target_create(struct target *target, Jim_Interp *interp)
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return ERROR_OK;
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}
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static uint32_t cortex_a8_get_ttb(struct target *target)
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{
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struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
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struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
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uint32_t ttb = 0, retval = ERROR_OK;
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/* current_address_mode is set inside cortex_a8_virt2phys()
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where we can determine if address belongs to user or kernel */
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if(cortex_a8->current_address_mode == ARM_MODE_SVC)
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{
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/* MRC p15,0,<Rt>,c1,c0,0 ; Read CP15 System Control Register */
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retval = armv7a->armv4_5_common.mrc(target, 15,
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0, 1, /* op1, op2 */
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2, 0, /* CRn, CRm */
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&ttb);
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}
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else if(cortex_a8->current_address_mode == ARM_MODE_USR)
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{
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/* MRC p15,0,<Rt>,c1,c0,0 ; Read CP15 System Control Register */
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retval = armv7a->armv4_5_common.mrc(target, 15,
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0, 0, /* op1, op2 */
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2, 0, /* CRn, CRm */
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&ttb);
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}
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/* we don't know whose address is: user or kernel
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we assume that if we are in kernel mode then
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address belongs to kernel else if in user mode
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- to user */
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else if(armv7a->armv4_5_common.core_mode == ARM_MODE_SVC)
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{
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/* MRC p15,0,<Rt>,c1,c0,0 ; Read CP15 System Control Register */
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retval = armv7a->armv4_5_common.mrc(target, 15,
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0, 1, /* op1, op2 */
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2, 0, /* CRn, CRm */
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&ttb);
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}
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else if(armv7a->armv4_5_common.core_mode == ARM_MODE_USR)
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{
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/* MRC p15,0,<Rt>,c1,c0,0 ; Read CP15 System Control Register */
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retval = armv7a->armv4_5_common.mrc(target, 15,
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0, 0, /* op1, op2 */
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2, 0, /* CRn, CRm */
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&ttb);
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}
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/* finaly we don't know whose ttb to use: user or kernel */
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else
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LOG_ERROR("Don't know how to get ttb for current mode!!!");
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ttb &= 0xffffc000;
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return ttb;
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}
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static void cortex_a8_disable_mmu_caches(struct target *target, int mmu,
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int d_u_cache, int i_cache)
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{
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struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
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struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
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uint32_t cp15_control;
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/* read cp15 control register */
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armv7a->armv4_5_common.mrc(target, 15,
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0, 0, /* op1, op2 */
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1, 0, /* CRn, CRm */
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&cp15_control);
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if (mmu)
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cp15_control &= ~0x1U;
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if (d_u_cache)
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cp15_control &= ~0x4U;
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if (i_cache)
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cp15_control &= ~0x1000U;
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armv7a->armv4_5_common.mcr(target, 15,
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0, 0, /* op1, op2 */
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1, 0, /* CRn, CRm */
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cp15_control);
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}
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static void cortex_a8_enable_mmu_caches(struct target *target, int mmu,
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int d_u_cache, int i_cache)
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{
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struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
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struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
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uint32_t cp15_control;
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/* read cp15 control register */
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armv7a->armv4_5_common.mrc(target, 15,
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0, 0, /* op1, op2 */
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1, 0, /* CRn, CRm */
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&cp15_control);
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if (mmu)
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cp15_control |= 0x1U;
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if (d_u_cache)
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cp15_control |= 0x4U;
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if (i_cache)
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cp15_control |= 0x1000U;
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armv7a->armv4_5_common.mcr(target, 15,
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0, 0, /* op1, op2 */
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1, 0, /* CRn, CRm */
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cp15_control);
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}
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static int cortex_a8_mmu(struct target *target, int *enabled)
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{
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if (target->state != TARGET_HALTED) {
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LOG_ERROR("%s: target not halted", __func__);
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return ERROR_TARGET_INVALID;
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}
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|
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*enabled = target_to_cortex_a8(target)->armv7a_common.armv4_5_mmu.mmu_enabled;
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
static int cortex_a8_virt2phys(struct target *target,
|
||||
uint32_t virt, uint32_t *phys)
|
||||
{
|
||||
int type;
|
||||
uint32_t cb;
|
||||
int domain;
|
||||
uint32_t ap;
|
||||
struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
|
||||
// struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
|
||||
struct armv7a_common *armv7a = target_to_armv7a(target);
|
||||
|
||||
/* We assume that virtual address is separated
|
||||
between user and kernel in Linux style:
|
||||
0x00000000-0xbfffffff - User space
|
||||
0xc0000000-0xffffffff - Kernel space */
|
||||
if( virt < 0xc0000000 ) /* Linux user space */
|
||||
cortex_a8->current_address_mode = ARM_MODE_USR;
|
||||
else /* Linux kernel */
|
||||
cortex_a8->current_address_mode = ARM_MODE_SVC;
|
||||
uint32_t ret = armv4_5_mmu_translate_va(target,
|
||||
&armv7a->armv4_5_mmu, virt, &type, &cb, &domain, &ap);
|
||||
/* Reset the flag. We don't want someone else to use it by error */
|
||||
cortex_a8->current_address_mode = ARM_MODE_ANY;
|
||||
|
||||
if (type == -1)
|
||||
{
|
||||
return ret;
|
||||
}
|
||||
*phys = ret;
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
COMMAND_HANDLER(cortex_a8_handle_cache_info_command)
|
||||
{
|
||||
struct target *target = get_current_target(CMD_CTX);
|
||||
|
|
@ -1703,4 +1917,10 @@ struct target_type cortexa8_target = {
|
|||
.target_create = cortex_a8_target_create,
|
||||
.init_target = cortex_a8_init_target,
|
||||
.examine = cortex_a8_examine,
|
||||
|
||||
.read_phys_memory = cortex_a8_read_phys_memory,
|
||||
.write_phys_memory = cortex_a8_write_phys_memory,
|
||||
.mmu = cortex_a8_mmu,
|
||||
.virt2phys = cortex_a8_virt2phys,
|
||||
|
||||
};
|
||||
|
|
|
|||
|
|
@ -72,6 +72,9 @@ struct cortex_a8_common
|
|||
/* Use cortex_a8_read_regs_through_mem for fast register reads */
|
||||
int fast_reg_read;
|
||||
|
||||
/* Flag that helps to resolve what ttb to use: user or kernel */
|
||||
int current_address_mode;
|
||||
|
||||
struct armv7a_common armv7a_common;
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue