From ce20be3d783882399047db1738e79b0a9ecdb1e8 Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Thu, 14 Sep 2017 16:21:49 -0700 Subject: [PATCH] Add support for F extension. --- src/target/riscv/program.c | 31 +++++++++++++++++++++++++++---- src/target/riscv/program.h | 4 ++-- src/target/riscv/riscv-013.c | 4 ++-- src/target/riscv/riscv.c | 2 ++ 4 files changed, 33 insertions(+), 8 deletions(-) diff --git a/src/target/riscv/program.c b/src/target/riscv/program.c index efad623e4..294e673ea 100644 --- a/src/target/riscv/program.c +++ b/src/target/riscv/program.c @@ -3,6 +3,7 @@ #endif #include "target/target.h" +#include "target/register.h" #include "riscv.h" #include "program.h" #include "helper/log.h" @@ -369,7 +370,7 @@ int riscv_program_addi(struct riscv_program *p, enum gdb_regno d, enum gdb_regno return riscv_program_insert(p, addi(d, s, u)); } -int riscv_program_fsd(struct riscv_program *p, enum gdb_regno d, riscv_addr_t addr) +int riscv_program_fsx(struct riscv_program *p, enum gdb_regno d, riscv_addr_t addr) { assert(d >= GDB_REGNO_FPR0); assert(d <= GDB_REGNO_FPR31); @@ -378,21 +379,43 @@ int riscv_program_fsd(struct riscv_program *p, enum gdb_regno d, riscv_addr_t ad : riscv_program_gettemp(p); if (riscv_program_lah(p, t, addr) != ERROR_OK) return ERROR_FAIL; - if (riscv_program_insert(p, fsd(d - GDB_REGNO_FPR0, t, riscv_program_gal(p, addr))) != ERROR_OK) + uint32_t instruction; + switch (p->target->reg_cache->reg_list[GDB_REGNO_FPR0].size) { + case 64: + instruction = fsd(d - GDB_REGNO_FPR0, t, riscv_program_gal(p, addr)); + break; + case 32: + instruction = fsw(d - GDB_REGNO_FPR0, t, riscv_program_gal(p, addr)); + break; + default: + return ERROR_FAIL; + } + if (riscv_program_insert(p, instruction) != ERROR_OK) return ERROR_FAIL; riscv_program_puttemp(p, t); p->writes_memory = true; return ERROR_OK; } -int riscv_program_fld(struct riscv_program *p, enum gdb_regno d, riscv_addr_t addr) +int riscv_program_flx(struct riscv_program *p, enum gdb_regno d, riscv_addr_t addr) { assert(d >= GDB_REGNO_FPR0); assert(d <= GDB_REGNO_FPR31); enum gdb_regno t = riscv_program_gah(p, addr) == 0 ? GDB_REGNO_X0 : d; if (riscv_program_lah(p, t, addr) != ERROR_OK) return ERROR_FAIL; - if (riscv_program_insert(p, fld(d - GDB_REGNO_FPR0, t, riscv_program_gal(p, addr))) != ERROR_OK) + uint32_t instruction; + switch (p->target->reg_cache->reg_list[GDB_REGNO_FPR0].size) { + case 64: + instruction = fld(d - GDB_REGNO_FPR0, t, riscv_program_gal(p, addr)); + break; + case 32: + instruction = flw(d - GDB_REGNO_FPR0, t, riscv_program_gal(p, addr)); + break; + default: + return ERROR_FAIL; + } + if (riscv_program_insert(p, instruction) != ERROR_OK) return ERROR_FAIL; return ERROR_OK; } diff --git a/src/target/riscv/program.h b/src/target/riscv/program.h index 1efdb125b..ac1127ed9 100644 --- a/src/target/riscv/program.h +++ b/src/target/riscv/program.h @@ -114,8 +114,8 @@ int riscv_program_ebreak(struct riscv_program *p); int riscv_program_lui(struct riscv_program *p, enum gdb_regno d, int32_t u); int riscv_program_addi(struct riscv_program *p, enum gdb_regno d, enum gdb_regno s, int16_t i); -int riscv_program_fsd(struct riscv_program *p, enum gdb_regno s, riscv_addr_t addr); -int riscv_program_fld(struct riscv_program *p, enum gdb_regno d, riscv_addr_t addr); +int riscv_program_fsx(struct riscv_program *p, enum gdb_regno s, riscv_addr_t addr); +int riscv_program_flx(struct riscv_program *p, enum gdb_regno d, riscv_addr_t addr); /* Assembler macros. */ int riscv_program_li(struct riscv_program *p, enum gdb_regno d, riscv_reg_t c); diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index 4ed87bc5e..8809483ff 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -780,7 +780,7 @@ static int register_write_direct(struct target *target, unsigned number, if (number <= GDB_REGNO_XPR31) { riscv_program_lx(&program, number, input); } else if (number >= GDB_REGNO_FPR0 && number <= GDB_REGNO_FPR31) { - riscv_program_fld(&program, number, input); + riscv_program_flx(&program, number, input); } else if (number >= GDB_REGNO_CSR0 && number <= GDB_REGNO_CSR4095) { enum gdb_regno temp = riscv_program_gettemp(&program); riscv_program_lx(&program, temp, input); @@ -816,7 +816,7 @@ static int register_read_direct(struct target *target, uint64_t *value, uint32_t if (number <= GDB_REGNO_XPR31) { riscv_program_sx(&program, number, output); } else if (number >= GDB_REGNO_FPR0 && number <= GDB_REGNO_FPR31) { - riscv_program_fsd(&program, number, output); + riscv_program_fsx(&program, number, output); } else if (number >= GDB_REGNO_CSR0 && number <= GDB_REGNO_CSR4095) { LOG_DEBUG("reading CSR index=0x%03x", number - GDB_REGNO_CSR0); enum gdb_regno temp = riscv_program_gettemp(&program); diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index 62628a179..a502da5a6 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -1715,6 +1715,8 @@ const char *gdb_regno_name(enum gdb_regno regno) sprintf(buf, "x%d", regno - GDB_REGNO_XPR0); } else if (regno >= GDB_REGNO_CSR0 && regno <= GDB_REGNO_CSR4095) { sprintf(buf, "csr%d", regno - GDB_REGNO_CSR0); + } else if (regno >= GDB_REGNO_FPR0 && regno <= GDB_REGNO_FPR31) { + sprintf(buf, "f%d", regno - GDB_REGNO_FPR0); } else { sprintf(buf, "gdb_regno_%d", regno); }