ARM ADIv5: "dap info" gets more readable
Make the "dap info" output more comprehensible: - Don't show CIDs unless they're incorrect (only four bits matter) - For CoreSight parts, interpret the part type - Interpret the part number - Show all five PID bytes together - Other minor cleanups Also some whitespace fixes, and shrink a few overlong source lines. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>__archive__
David Brownell
parent
8f3b28ff41
commit
ddade10d4a
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@ -1007,11 +1007,20 @@ int ahbap_debugport_init(swjdp_common_t *swjdp)
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return ERROR_OK;
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}
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/* CID interpretation -- see ARM IHI 0029B section 3 */
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static const char *class_description[16] ={
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"Reserved", "ROM table", "Reserved", "Reserved",
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"Reserved", "Reserved", "Reserved", "Reserved",
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"Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
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"Reserved", "DESS", "Generic IP component", "PrimeCell or System component"
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};
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char * class_description[16] ={
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"Reserved",
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"ROM table","Reserved","Reserved","Reserved","Reserved","Reserved","Reserved","Reserved",
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"CoreSight component","Reserved","Peripheral Test Block","Reserved","DESS","Generic IP component","Non standard layout"};
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static bool
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is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
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{
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return cid3 == 0xb1 && cid2 == 0x05
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&& ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
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}
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int dap_info_command(struct command_context_s *cmd_ctx, swjdp_common_t *swjdp, int apsel)
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{
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@ -1058,15 +1067,13 @@ int dap_info_command(struct command_context_s *cmd_ctx, swjdp_common_t *swjdp, i
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{
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uint32_t cid0,cid1,cid2,cid3,memtype,romentry;
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uint16_t entry_offset;
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/* bit 16 of apid indicates a memory access port */
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if (dbgbase&0x02)
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{
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if (dbgbase & 0x02)
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command_print(cmd_ctx, "\tValid ROM table present");
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}
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else
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{
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command_print(cmd_ctx, "\tROM table in legacy format");
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}
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/* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
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mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
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mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
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@ -1074,15 +1081,17 @@ int dap_info_command(struct command_context_s *cmd_ctx, swjdp_common_t *swjdp, i
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mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
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mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
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swjdp_transaction_endcheck(swjdp);
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command_print(cmd_ctx, "\tCID3 0x%" PRIx32 ", CID2 0x%" PRIx32 ", CID1 0x%" PRIx32 " CID0, 0x%" PRIx32,cid3,cid2,cid1,cid0);
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if (memtype&0x01)
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{
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if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
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command_print(cmd_ctx, "\tCID3 0x%2.2" PRIx32
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", CID2 0x%2.2" PRIx32
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", CID1 0x%2.2" PRIx32
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", CID0 0x%2.2" PRIx32,
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cid3, cid2, cid1, cid0);
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if (memtype & 0x01)
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command_print(cmd_ctx, "\tMEMTYPE system memory present on bus");
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}
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else
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{
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command_print(cmd_ctx, "\tMEMTYPE system memory not present. Dedicated debug bus");
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}
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command_print(cmd_ctx, "\tMEMTYPE System memory not present. "
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"Dedicated debug bus.");
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/* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
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entry_offset = 0;
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@ -1092,23 +1101,249 @@ int dap_info_command(struct command_context_s *cmd_ctx, swjdp_common_t *swjdp, i
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command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "",entry_offset,romentry);
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if (romentry&0x01)
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{
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uint32_t c_cid0,c_cid1,c_cid2,c_cid3,c_pid0,c_pid1,c_pid2,c_pid3,c_pid4,component_start;
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uint32_t component_base = (uint32_t)((dbgbase&0xFFFFF000) + (int)(romentry&0xFFFFF000));
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mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000) | 0xFE0, &c_pid0);
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mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000) | 0xFE4, &c_pid1);
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mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000) | 0xFE8, &c_pid2);
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mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000) | 0xFEC, &c_pid3);
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mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000) | 0xFD0, &c_pid4);
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mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000) | 0xFF0, &c_cid0);
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mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000) | 0xFF4, &c_cid1);
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mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000) | 0xFF8, &c_cid2);
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mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000) | 0xFFC, &c_cid3);
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uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
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uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
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uint32_t component_start, component_base;
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unsigned part_num;
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char *type, *full;
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component_base = (uint32_t)((dbgbase & 0xFFFFF000)
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+ (int)(romentry & 0xFFFFF000));
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mem_ap_read_atomic_u32(swjdp,
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(component_base & 0xFFFFF000) | 0xFE0, &c_pid0);
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mem_ap_read_atomic_u32(swjdp,
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(component_base & 0xFFFFF000) | 0xFE4, &c_pid1);
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mem_ap_read_atomic_u32(swjdp,
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(component_base & 0xFFFFF000) | 0xFE8, &c_pid2);
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mem_ap_read_atomic_u32(swjdp,
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(component_base & 0xFFFFF000) | 0xFEC, &c_pid3);
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mem_ap_read_atomic_u32(swjdp,
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(component_base & 0xFFFFF000) | 0xFD0, &c_pid4);
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mem_ap_read_atomic_u32(swjdp,
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(component_base & 0xFFFFF000) | 0xFF0, &c_cid0);
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mem_ap_read_atomic_u32(swjdp,
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(component_base & 0xFFFFF000) | 0xFF4, &c_cid1);
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mem_ap_read_atomic_u32(swjdp,
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(component_base & 0xFFFFF000) | 0xFF8, &c_cid2);
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mem_ap_read_atomic_u32(swjdp,
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(component_base & 0xFFFFF000) | 0xFFC, &c_cid3);
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component_start = component_base - 0x1000*(c_pid4 >> 4);
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command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32 ", pid4 0x%" PRIx32 ", start address 0x%" PRIx32 "",component_base,c_pid4,component_start);
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command_print(cmd_ctx, "\t\tComponent cid1 0x%" PRIx32 ", class is %s",c_cid1,class_description[(c_cid1 >> 4)&0xF]); /* Se ARM DDI 0314 C Table 2.2 */
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command_print(cmd_ctx, "\t\tCID3 0x%" PRIx32 ", CID2 0x%" PRIx32 ", CID1 0x%" PRIx32 ", CID0, 0x%" PRIx32 "",c_cid3,c_cid2,c_cid1,c_cid0);
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command_print(cmd_ctx, "\t\tPID3 0x%" PRIx32 ", PID2 0x%" PRIx32 ", PID1 0x%" PRIx32 ", PID0, 0x%" PRIx32 "",c_pid3,c_pid2,c_pid1,c_pid0);
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/* For CoreSight components, (c_cid1 >> 4)&0xF == 9 , we also read 0xFC8 DevId and 0xFCC DevType */
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command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32
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", start address 0x%" PRIx32,
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component_base, component_start);
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command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s",
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(int) (c_cid1 >> 4) & 0xf,
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/* See ARM IHI 0029B Table 3-3 */
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class_description[(c_cid1 >> 4) & 0xf]);
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/* CoreSight component? */
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if (((c_cid1 >> 4) & 0x0f) == 9) {
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uint32_t devtype;
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unsigned minor;
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char *major = "Reserved", *subtype = "Reserved";
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mem_ap_read_atomic_u32(swjdp,
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(component_base & 0xfffff000) | 0xfcc,
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&devtype);
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minor = (devtype >> 4) & 0x0f;
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switch (devtype & 0x0f) {
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case 0:
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major = "Miscellaneous";
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switch (minor) {
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case 0:
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subtype = "other";
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break;
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case 4:
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subtype = "Validation component";
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break;
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}
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break;
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case 1:
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major = "Trace Sink";
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switch (minor) {
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case 0:
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subtype = "other";
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break;
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case 1:
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subtype = "Port";
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break;
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case 2:
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subtype = "Buffer";
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break;
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}
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break;
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case 2:
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major = "Trace Link";
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switch (minor) {
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case 0:
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subtype = "other";
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break;
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case 1:
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subtype = "Funnel, router";
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break;
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case 2:
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subtype = "Filter";
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break;
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case 3:
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subtype = "FIFO, buffer";
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break;
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}
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break;
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case 3:
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major = "Trace Source";
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switch (minor) {
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case 0:
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subtype = "other";
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break;
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case 1:
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subtype = "Processor";
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break;
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case 2:
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subtype = "DSP";
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break;
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case 3:
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subtype = "Engine/Coprocessor";
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break;
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case 4:
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subtype = "Bus";
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break;
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}
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break;
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case 4:
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major = "Debug Control";
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switch (minor) {
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case 0:
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subtype = "other";
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break;
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case 1:
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subtype = "Trigger Matrix";
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break;
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case 2:
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subtype = "Debug Auth";
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break;
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}
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break;
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case 5:
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major = "Debug Logic";
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switch (minor) {
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case 0:
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subtype = "other";
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break;
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case 1:
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subtype = "Processor";
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break;
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case 2:
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subtype = "DSP";
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break;
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case 3:
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subtype = "Engine/Coprocessor";
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break;
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}
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break;
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}
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command_print(cmd_ctx, "\t\tType is 0x%2.2x, %s, %s",
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(unsigned) (devtype & 0xff),
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major, subtype);
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/* REVISIT also show 0xfc8 DevId */
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}
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if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
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command_print(cmd_ctx, "\t\tCID3 0x%2.2" PRIx32
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", CID2 0x%2.2" PRIx32
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", CID1 0x%2.2" PRIx32
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", CID0 0x%2.2" PRIx32,
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c_cid3, c_cid2, c_cid1, c_cid0);
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command_print(cmd_ctx, "\t\tPeripheral ID[4..0] = hex "
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"%2.2x %2.2x %2.2x %2.2x %2.2x",
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(int) c_pid4,
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(int) c_pid3, (int) c_pid2,
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(int) c_pid1, (int) c_pid0);
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/* Part number interpretations are from Cortex
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* core specs, the CoreSight components TRM
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* (ARM DDI 0314H), and ETM specs; also from
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* chip observation (e.g. TI SDTI).
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*/
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part_num = c_pid0 & 0xff;
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part_num |= (c_pid1 & 0x0f) << 8;
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switch (part_num) {
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case 0x000:
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type = "Cortex-M3 NVIC";
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full = "(Interrupt Controller)";
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break;
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case 0x001:
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type = "Cortex-M3 ITM";
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full = "(Instrumentation Trace Module)";
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break;
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case 0x002:
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type = "Cortex-M3 DWT";
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full = "(Data Watchpoint and Trace)";
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break;
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case 0x003:
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type = "Cortex-M3 FBP";
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full = "(Flash Patch and Breakpoint)";
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break;
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case 0x00d:
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type = "CoreSight ETM11";
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full = "(Embedded Trace)";
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break;
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// case 0x113: what?
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case 0x120: /* from OMAP3 memmap */
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type = "TI SDTI";
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full = "(System Debug Trace Interface)";
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break;
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case 0x343: /* from OMAP3 memmap */
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type = "TI DAPCTL";
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full = "";
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break;
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case 0x4e0:
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type = "Cortex-M3 ETM";
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full = "(Embedded Trace)";
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break;
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case 0x906:
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type = "Coresight CTI";
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full = "(Cross Trigger)";
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break;
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case 0x907:
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type = "Coresight ETB";
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full = "(Trace Buffer)";
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break;
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case 0x908:
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type = "Coresight CSTF";
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full = "(Trace Funnel)";
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break;
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case 0x910:
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type = "CoreSight ETM9";
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full = "(Embedded Trace)";
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break;
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case 0x912:
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type = "Coresight TPIU";
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full = "(Trace Port Interface Unit)";
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break;
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case 0x921:
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type = "Cortex-A8 ETM";
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full = "(Embedded Trace)";
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break;
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case 0x922:
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type = "Cortex-A8 CTI";
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full = "(Cross Trigger)";
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break;
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case 0x923:
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type = "Cortex-M3 TPIU";
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full = "(Trace Port Interface Unit)";
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break;
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case 0xc08:
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type = "Cortex-A8 Debug";
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full = "(Debug Unit)";
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break;
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default:
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type = "-*- unrecognized -*-";
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full = "";
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break;
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}
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command_print(cmd_ctx, "\t\tPart is %s %s",
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type, full);
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}
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else
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{
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