at91sam4: Add missing SAM4S family CHIPIDs and remove FWS=6.
Add missing CHIPID values for all SAM4S parts listed in revision K of Atmel-11100-32-bit Cortex-M4-Microcontroller-SAM4S_Datasheet.pdf. I have also removed the FWS=6 workaround, as this appears to be a copy-paste error from the SAM3X family. Change-Id: I1ce1d82911f39d6fcb8f04034f5c9c9bf2818466 Signed-off-by: Owen Kirby <oskirby@gmail.com> Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/3837 Tested-by: jenkinsgitignore-build
parent
c591f109c3
commit
dc0a009ef4
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@ -666,7 +666,7 @@ static const struct sam4_chip_details all_sam4_details[] = {
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.bank_number = 0,
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.base_address = FLASH_BANK_BASE_S,
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.controller_address = 0x400e0a00,
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.flash_wait_states = 6, /* workaround silicon bug */
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.flash_wait_states = 5,
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.present = 1,
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.size_bytes = 1024 * 1024,
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.nsectors = 128,
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@ -682,7 +682,7 @@ static const struct sam4_chip_details all_sam4_details[] = {
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},
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},
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},
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/*atsam4s16b - LQFP64/QFN64*/
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/*atsam4s16b - LQFP64/QFN64/WLCSP64*/
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{
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.chipid_cidr = 0x289C0CE0,
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.name = "at91sam4s16b",
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@ -699,7 +699,7 @@ static const struct sam4_chip_details all_sam4_details[] = {
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.bank_number = 0,
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.base_address = FLASH_BANK_BASE_S,
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.controller_address = 0x400e0a00,
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.flash_wait_states = 6, /* workaround silicon bug */
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.flash_wait_states = 5,
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.present = 1,
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.size_bytes = 1024 * 1024,
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.nsectors = 128,
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@ -732,7 +732,7 @@ static const struct sam4_chip_details all_sam4_details[] = {
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.bank_number = 0,
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.base_address = FLASH_BANK_BASE_S,
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.controller_address = 0x400e0a00,
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.flash_wait_states = 6, /* workaround silicon bug */
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.flash_wait_states = 5,
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.present = 1,
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.size_bytes = 1024 * 1024,
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.nsectors = 128,
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@ -765,7 +765,7 @@ static const struct sam4_chip_details all_sam4_details[] = {
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.bank_number = 0,
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.base_address = FLASH_BANK_BASE_S,
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.controller_address = 0x400e0a00,
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.flash_wait_states = 6, /* workaround silicon bug */
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.flash_wait_states = 5,
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.present = 1,
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.size_bytes = 1024 * 1024,
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.nsectors = 128,
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@ -798,7 +798,7 @@ static const struct sam4_chip_details all_sam4_details[] = {
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.bank_number = 0,
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.base_address = FLASH_BANK_BASE_S,
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.controller_address = 0x400e0a00,
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.flash_wait_states = 6, /* workaround silicon bug */
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.flash_wait_states = 5,
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.present = 1,
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.size_bytes = 512 * 1024,
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.nsectors = 64,
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@ -814,7 +814,7 @@ static const struct sam4_chip_details all_sam4_details[] = {
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},
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},
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},
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/*atsam4s8b - LQFP64/BGA64*/
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/*atsam4s8b - LQFP64/QFN64/WLCSP64*/
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{
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.chipid_cidr = 0x289C0AE0,
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.name = "at91sam4s8b",
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@ -831,7 +831,7 @@ static const struct sam4_chip_details all_sam4_details[] = {
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.bank_number = 0,
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.base_address = FLASH_BANK_BASE_S,
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.controller_address = 0x400e0a00,
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.flash_wait_states = 6, /* workaround silicon bug */
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.flash_wait_states = 5,
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.present = 1,
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.size_bytes = 512 * 1024,
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.nsectors = 64,
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@ -864,7 +864,7 @@ static const struct sam4_chip_details all_sam4_details[] = {
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.bank_number = 0,
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.base_address = FLASH_BANK_BASE_S,
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.controller_address = 0x400e0a00,
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.flash_wait_states = 6, /* workaround silicon bug */
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.flash_wait_states = 5,
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.present = 1,
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.size_bytes = 512 * 1024,
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.nsectors = 64,
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@ -881,10 +881,10 @@ static const struct sam4_chip_details all_sam4_details[] = {
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},
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},
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/*atsam4s4a - LQFP48/BGA48*/
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/*atsam4s4c - LQFP100/BGA100*/
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{
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.chipid_cidr = 0x288b09e0,
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.name = "at91sam4s4a",
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.chipid_cidr = 0x28ab09e0,
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.name = "at91sam4s4c",
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.total_flash_size = 256 * 1024,
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.total_sram_size = 64 * 1024,
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.n_gpnvms = 2,
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@ -898,7 +898,7 @@ static const struct sam4_chip_details all_sam4_details[] = {
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.bank_number = 0,
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.base_address = FLASH_BANK_BASE_S,
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.controller_address = 0x400e0a00,
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.flash_wait_states = 6, /* workaround silicon bug */
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.flash_wait_states = 5,
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.present = 1,
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.size_bytes = 256 * 1024,
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.nsectors = 32,
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@ -915,7 +915,177 @@ static const struct sam4_chip_details all_sam4_details[] = {
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},
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},
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/*at91sam4sd32c*/
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/*atsam4s4b - LQFP64/QFN64/WLCSP64*/
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{
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.chipid_cidr = 0x289b09e0,
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.name = "at91sam4s4b",
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.total_flash_size = 256 * 1024,
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.total_sram_size = 64 * 1024,
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.n_gpnvms = 2,
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.n_banks = 1,
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{
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/* .bank[0] = {*/
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{
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.probed = 0,
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.pChip = NULL,
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.pBank = NULL,
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.bank_number = 0,
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.base_address = FLASH_BANK_BASE_S,
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.controller_address = 0x400e0a00,
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.flash_wait_states = 5,
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.present = 1,
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.size_bytes = 256 * 1024,
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.nsectors = 32,
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.sector_size = 8192,
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.page_size = 512,
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},
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/* .bank[1] = {*/
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{
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.present = 0,
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.probed = 0,
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.bank_number = 1,
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},
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},
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},
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/*atsam4s4a - LQFP48/QFN48*/
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{
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.chipid_cidr = 0x288b09e0,
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.name = "at91sam4s4a",
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.total_flash_size = 256 * 1024,
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.total_sram_size = 64 * 1024,
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.n_gpnvms = 2,
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.n_banks = 1,
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{
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/* .bank[0] = {*/
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{
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.probed = 0,
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.pChip = NULL,
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.pBank = NULL,
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.bank_number = 0,
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.base_address = FLASH_BANK_BASE_S,
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.controller_address = 0x400e0a00,
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.flash_wait_states = 5,
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.present = 1,
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.size_bytes = 256 * 1024,
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.nsectors = 32,
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.sector_size = 8192,
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.page_size = 512,
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},
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/* .bank[1] = {*/
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{
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.present = 0,
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.probed = 0,
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.bank_number = 1,
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},
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},
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},
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/*atsam4s2c - LQFP100/BGA100*/
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{
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.chipid_cidr = 0x28ab07e0,
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.name = "at91sam4s2c",
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.total_flash_size = 128 * 1024,
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.total_sram_size = 64 * 1024,
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.n_gpnvms = 2,
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.n_banks = 1,
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{
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/* .bank[0] = {*/
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{
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.probed = 0,
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.pChip = NULL,
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.pBank = NULL,
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.bank_number = 0,
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.base_address = FLASH_BANK_BASE_S,
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.controller_address = 0x400e0a00,
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.flash_wait_states = 5,
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.present = 1,
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.size_bytes = 128 * 1024,
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.nsectors = 16,
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.sector_size = 8192,
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.page_size = 512,
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},
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/* .bank[1] = {*/
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{
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.present = 0,
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.probed = 0,
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.bank_number = 1,
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},
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},
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},
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/*atsam4s2b - LQPF64/QFN64/WLCSP64*/
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{
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.chipid_cidr = 0x289b07e0,
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.name = "at91sam4s2b",
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.total_flash_size = 128 * 1024,
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.total_sram_size = 64 * 1024,
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.n_gpnvms = 2,
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.n_banks = 1,
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{
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/* .bank[0] = {*/
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{
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.probed = 0,
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.pChip = NULL,
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.pBank = NULL,
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.bank_number = 0,
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.base_address = FLASH_BANK_BASE_S,
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.controller_address = 0x400e0a00,
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.flash_wait_states = 5,
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.present = 1,
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.size_bytes = 128 * 1024,
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.nsectors = 16,
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.sector_size = 8192,
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.page_size = 512,
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},
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/* .bank[1] = {*/
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{
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.present = 0,
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.probed = 0,
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.bank_number = 1,
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},
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},
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},
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/*atsam4s2a - LQFP48/QFN48*/
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{
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.chipid_cidr = 0x288b07e0,
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.name = "at91sam4s2a",
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.total_flash_size = 128 * 1024,
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.total_sram_size = 64 * 1024,
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.n_gpnvms = 2,
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.n_banks = 1,
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{
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/* .bank[0] = {*/
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{
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.probed = 0,
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.pChip = NULL,
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.pBank = NULL,
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.bank_number = 0,
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.base_address = FLASH_BANK_BASE_S,
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.controller_address = 0x400e0a00,
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.flash_wait_states = 5,
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.present = 1,
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.size_bytes = 128 * 1024,
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.nsectors = 16,
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.sector_size = 8192,
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.page_size = 512,
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},
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/* .bank[1] = {*/
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{
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.present = 0,
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.probed = 0,
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.bank_number = 1,
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},
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},
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},
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/*at91sam4sd32c - LQFP100/BGA100*/
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{
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.chipid_cidr = 0x29a70ee0,
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.name = "at91sam4sd32c",
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@ -933,7 +1103,7 @@ static const struct sam4_chip_details all_sam4_details[] = {
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.bank_number = 0,
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.base_address = FLASH_BANK0_BASE_SD,
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.controller_address = 0x400e0a00,
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.flash_wait_states = 6, /* workaround silicon bug */
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.flash_wait_states = 5,
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.present = 1,
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.size_bytes = 1024 * 1024,
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.nsectors = 128,
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@ -949,7 +1119,7 @@ static const struct sam4_chip_details all_sam4_details[] = {
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.bank_number = 1,
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.base_address = FLASH_BANK1_BASE_2048K_SD,
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.controller_address = 0x400e0c00,
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.flash_wait_states = 6, /* workaround silicon bug */
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.flash_wait_states = 5,
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.present = 1,
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.size_bytes = 1024 * 1024,
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.nsectors = 128,
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@ -959,7 +1129,51 @@ static const struct sam4_chip_details all_sam4_details[] = {
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},
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},
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/*at91sam4sd16c*/
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/*at91sam4sd32b - LQFP64/BGA64*/
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{
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.chipid_cidr = 0x29970ee0,
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.name = "at91sam4sd32b",
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.total_flash_size = 2048 * 1024,
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.total_sram_size = 160 * 1024,
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.n_gpnvms = 3,
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.n_banks = 2,
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/* .bank[0] = { */
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{
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{
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.probed = 0,
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.pChip = NULL,
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.pBank = NULL,
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.bank_number = 0,
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.base_address = FLASH_BANK0_BASE_SD,
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.controller_address = 0x400e0a00,
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.flash_wait_states = 5,
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.present = 1,
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.size_bytes = 1024 * 1024,
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.nsectors = 128,
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.sector_size = 8192,
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.page_size = 512,
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},
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/* .bank[1] = { */
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{
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.probed = 0,
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.pChip = NULL,
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.pBank = NULL,
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.bank_number = 1,
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.base_address = FLASH_BANK1_BASE_2048K_SD,
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.controller_address = 0x400e0c00,
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.flash_wait_states = 5,
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.present = 1,
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.size_bytes = 1024 * 1024,
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.nsectors = 128,
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.sector_size = 8192,
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.page_size = 512,
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},
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},
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},
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/*at91sam4sd16c - LQFP100/BGA100*/
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{
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.chipid_cidr = 0x29a70ce0,
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.name = "at91sam4sd16c",
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@ -977,7 +1191,7 @@ static const struct sam4_chip_details all_sam4_details[] = {
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.bank_number = 0,
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.base_address = FLASH_BANK0_BASE_SD,
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.controller_address = 0x400e0a00,
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.flash_wait_states = 6, /* workaround silicon bug */
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.flash_wait_states = 5,
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.present = 1,
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.size_bytes = 512 * 1024,
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.nsectors = 64,
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@ -993,7 +1207,51 @@ static const struct sam4_chip_details all_sam4_details[] = {
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.bank_number = 1,
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.base_address = FLASH_BANK1_BASE_1024K_SD,
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.controller_address = 0x400e0c00,
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.flash_wait_states = 6, /* workaround silicon bug */
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.flash_wait_states = 5,
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.present = 1,
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.size_bytes = 512 * 1024,
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.nsectors = 64,
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.sector_size = 8192,
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.page_size = 512,
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},
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},
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},
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/*at91sam4sd16b - LQFP64/BGA64*/
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{
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.chipid_cidr = 0x29970ce0,
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.name = "at91sam4sd16b",
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.total_flash_size = 1024 * 1024,
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.total_sram_size = 160 * 1024,
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.n_gpnvms = 3,
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.n_banks = 2,
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/* .bank[0] = { */
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{
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{
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.probed = 0,
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.pChip = NULL,
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.pBank = NULL,
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.bank_number = 0,
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.base_address = FLASH_BANK0_BASE_SD,
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.controller_address = 0x400e0a00,
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.flash_wait_states = 5,
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.present = 1,
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.size_bytes = 512 * 1024,
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.nsectors = 64,
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.sector_size = 8192,
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.page_size = 512,
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},
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/* .bank[1] = { */
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{
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.probed = 0,
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.pChip = NULL,
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.pBank = NULL,
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.bank_number = 1,
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.base_address = FLASH_BANK1_BASE_1024K_SD,
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.controller_address = 0x400e0c00,
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.flash_wait_states = 5,
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.present = 1,
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.size_bytes = 512 * 1024,
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.nsectors = 64,
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