allow minidrivers to implement inner loop of dcc memory writes
git-svn-id: svn://svn.berlios.de/openocd/trunk@879 b42882b7-edfa-0310-969c-e2dbd0fdcd60__archive__
oharboe
parent
0f18744a87
commit
db7c3810c2
File diff suppressed because it is too large
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@ -39,7 +39,7 @@
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#include <stdlib.h>
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bitfield_desc_t embeddedice_comms_ctrl_bitfield_desc[] =
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bitfield_desc_t embeddedice_comms_ctrl_bitfield_desc[] =
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{
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{"R", 1},
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{"W", 1},
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@ -59,24 +59,24 @@ char* embeddedice_reg_list[] =
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{
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"debug_ctrl",
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"debug_status",
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"comms_ctrl",
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"comms_data",
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"watch 0 addr value",
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"watch 0 addr mask",
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"watch 0 data value",
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"watch 0 data mask",
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"watch 0 control value",
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"watch 0 control mask",
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"watch 1 addr value",
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"watch 1 addr mask",
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"watch 1 data value",
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"watch 1 data mask",
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"watch 1 control value",
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"watch 1 control mask",
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"vector catch"
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};
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@ -99,26 +99,26 @@ reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7
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int num_regs;
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int i;
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int eice_version = 0;
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/* register a register arch-type for EmbeddedICE registers only once */
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if (embeddedice_reg_arch_type == -1)
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embeddedice_reg_arch_type = register_reg_arch_type(embeddedice_get_reg, embeddedice_set_reg_w_exec);
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if (arm7_9->has_vector_catch)
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num_regs = 17;
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else
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num_regs = 16;
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/* the actual registers are kept in two arrays */
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reg_list = calloc(num_regs, sizeof(reg_t));
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arch_info = calloc(num_regs, sizeof(embeddedice_reg_t));
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/* fill in values for the reg cache */
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reg_cache->name = "EmbeddedICE registers";
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reg_cache->next = NULL;
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reg_cache->reg_list = reg_list;
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reg_cache->num_regs = num_regs;
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/* set up registers */
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for (i = 0; i < num_regs; i++)
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{
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@ -134,7 +134,7 @@ reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7
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arch_info[i].addr = embeddedice_reg_arch_info[i];
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arch_info[i].jtag_info = jtag_info;
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}
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/* identify EmbeddedICE version by reading DCC control register */
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embeddedice_read_reg(®_list[EICE_COMMS_CTRL]);
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if ((retval=jtag_execute_queue())!=ERROR_OK)
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@ -147,9 +147,9 @@ reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7
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free(arch_info);
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return NULL;
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}
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eice_version = buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 28, 4);
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switch (eice_version)
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{
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case 1:
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@ -162,7 +162,7 @@ reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7
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arm7_9->has_single_step = 1;
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break;
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case 3:
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LOG_ERROR("EmbeddedICE version 3 detected, EmbeddedICE handling might be broken");
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LOG_ERROR("EmbeddedICE version 3 detected, EmbeddedICE handling might be broken");
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reg_list[EICE_DBG_CTRL].size = 6;
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reg_list[EICE_DBG_STAT].size = 5;
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arm7_9->has_single_step = 1;
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@ -193,7 +193,7 @@ reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7
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default:
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LOG_ERROR("unknown EmbeddedICE version (comms ctrl: 0x%8.8x)", buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 0, 32));
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}
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return reg_cache;
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}
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@ -202,12 +202,12 @@ int embeddedice_setup(target_t *target)
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int retval;
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armv4_5_common_t *armv4_5 = target->arch_info;
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arm7_9_common_t *arm7_9 = armv4_5->arch_info;
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/* explicitly disable monitor mode */
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if (arm7_9->has_monitor_mode)
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{
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reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
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embeddedice_read_reg(dbg_ctrl);
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if ((retval=jtag_execute_queue())!=ERROR_OK)
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return retval;
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@ -224,12 +224,12 @@ int embeddedice_get_reg(reg_t *reg)
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LOG_ERROR("BUG: error scheduling EmbeddedICE register read");
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exit(-1);
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}
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if (jtag_execute_queue() != ERROR_OK)
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{
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LOG_ERROR("register read failed");
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}
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return ERROR_OK;
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}
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@ -243,9 +243,9 @@ int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
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jtag_add_end_state(TAP_RTI);
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arm_jtag_scann(ice_reg->jtag_info, 0x2);
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arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);
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fields[0].device = ice_reg->jtag_info->chain_pos;
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fields[0].num_bits = 32;
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fields[0].out_value = reg->value;
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@ -255,7 +255,7 @@ int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
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fields[0].in_check_mask = NULL;
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fields[0].in_handler = NULL;
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fields[0].in_handler_priv = NULL;
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fields[1].device = ice_reg->jtag_info->chain_pos;
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fields[1].num_bits = 5;
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fields[1].out_value = field1_out;
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@ -277,18 +277,18 @@ int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
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fields[2].in_check_mask = NULL;
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fields[2].in_handler = NULL;
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fields[2].in_handler_priv = NULL;
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jtag_add_dr_scan(3, fields, -1);
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fields[0].in_value = reg->value;
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jtag_set_check_value(fields+0, check_value, check_mask, NULL);
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/* when reading the DCC data register, leaving the address field set to
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* EICE_COMMS_DATA would read the register twice
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* reading the control register is safe
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*/
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buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
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jtag_add_dr_scan(3, fields, -1);
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return ERROR_OK;
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@ -307,7 +307,7 @@ int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size)
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jtag_add_end_state(TAP_RTI);
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arm_jtag_scann(jtag_info, 0x2);
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arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
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fields[0].device = jtag_info->chain_pos;
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fields[0].num_bits = 32;
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fields[0].out_value = NULL;
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@ -317,7 +317,7 @@ int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size)
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fields[0].in_check_mask = NULL;
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fields[0].in_handler = NULL;
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fields[0].in_handler_priv = NULL;
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fields[1].device = jtag_info->chain_pos;
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fields[1].num_bits = 5;
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fields[1].out_value = field1_out;
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@ -339,9 +339,9 @@ int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size)
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fields[2].in_check_mask = NULL;
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fields[2].in_handler = NULL;
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fields[2].in_handler_priv = NULL;
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jtag_add_dr_scan(3, fields, -1);
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while (size > 0)
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{
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/* when reading the last item, set the register address to the DCC control reg,
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@ -349,21 +349,21 @@ int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size)
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*/
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if (size == 1)
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buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
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fields[0].in_handler = arm_jtag_buf_to_u32;
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fields[0].in_handler_priv = data;
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jtag_add_dr_scan(3, fields, -1);
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data++;
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size--;
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}
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return jtag_execute_queue();
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}
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int embeddedice_read_reg(reg_t *reg)
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{
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return embeddedice_read_reg_w_check(reg, NULL, NULL);
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return embeddedice_read_reg_w_check(reg, NULL, NULL);
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}
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int embeddedice_set_reg(reg_t *reg, u32 value)
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@ -373,18 +373,18 @@ int embeddedice_set_reg(reg_t *reg, u32 value)
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LOG_ERROR("BUG: error scheduling EmbeddedICE register write");
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exit(-1);
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}
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buf_set_u32(reg->value, 0, reg->size, value);
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reg->valid = 1;
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reg->dirty = 0;
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return ERROR_OK;
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}
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int embeddedice_set_reg_w_exec(reg_t *reg, u8 *buf)
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{
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embeddedice_set_reg(reg, buf_get_u32(buf, 0, reg->size));
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if (jtag_execute_queue() != ERROR_OK)
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{
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LOG_ERROR("register write failed");
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@ -398,15 +398,15 @@ int embeddedice_write_reg(reg_t *reg, u32 value)
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embeddedice_reg_t *ice_reg = reg->arch_info;
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LOG_DEBUG("%i: 0x%8.8x", ice_reg->addr, value);
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jtag_add_end_state(TAP_RTI);
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arm_jtag_scann(ice_reg->jtag_info, 0x2);
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arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);
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u8 reg_addr = ice_reg->addr & 0x1f;
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embeddedice_write_reg_inner(ice_reg->jtag_info->chain_pos, reg_addr, value);
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return ERROR_OK;
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}
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@ -548,3 +548,14 @@ int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, u32 timeout)
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return ERROR_TARGET_TIMEOUT;
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}
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/* this is the inner loop of the open loop DCC write of data to target */
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void MINIDRIVER(embeddedice_write_dcc)(int chain_pos, int reg_addr, u8 *buffer, int little, int count)
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{
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int i;
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for (i = 0; i < count; i++)
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{
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embeddedice_write_reg_inner(chain_pos, reg_addr, fast_target_buffer_get_u32(buffer, little));
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buffer += 4;
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}
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}
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@ -52,7 +52,7 @@ enum
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enum
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{
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EICE_DBG_CONTROL_ICEDIS = 5,
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EICE_DBG_CONTROL_MONEN = 4,
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EICE_DBG_CONTROL_MONEN = 4,
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EICE_DBG_CONTROL_INTDIS = 2,
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EICE_DBG_CONTROL_DBGRQ = 1,
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EICE_DBG_CONTROL_DBGACK = 0,
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@ -105,24 +105,26 @@ extern int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size);
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extern int embeddedice_send(arm_jtag_t *jtag_info, u32 *data, u32 size);
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extern int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, u32 timeout);
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/* If many embeddedice_write_reg() follow eachother, then the >1 invocations can be this faster version of
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/* If many embeddedice_write_reg() follow eachother, then the >1 invocations can be this faster version of
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* embeddedice_write_reg
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*/
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static const int embeddedice_num_bits[]={32,5,1};
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static __inline__ void embeddedice_write_reg_inner(int chain_pos, int reg_addr, u32 value)
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{
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u32 values[3];
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values[0]=value;
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values[1]=reg_addr;
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values[2]=1;
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jtag_add_dr_out(chain_pos,
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jtag_add_dr_out(chain_pos,
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3,
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embeddedice_num_bits,
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values,
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-1);
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}
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void embeddedice_write_dcc(int chain_pos, int reg_addr, u8 *buffer, int little, int count);
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#endif /* EMBEDDED_ICE_H */
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