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riscv: Fix some blocking compile warnings

race
Megan Wachs 2017-04-26 10:21:56 -07:00 committed by Palmer Dabbelt
parent 1ab5d7b497
commit da66be0161
2 changed files with 7 additions and 5 deletions
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8
src/flash/nor/fespi.c
View File

@ -189,7 +189,9 @@ FLASH_BANK_COMMAND_HANDLER(fespi_flash_bank_command)
fespi_info->probed = 0; fespi_info->probed = 0;
fespi_info->ctrl_base = 0; fespi_info->ctrl_base = 0;
if (CMD_ARGC >= 6) { if (CMD_ARGC >= 6) {
COMMAND_PARSE_NUMBER(int, CMD_ARGV[6], fespi_info->ctrl_base); int temp;
COMMAND_PARSE_NUMBER(int, CMD_ARGV[6], temp);
fespi_info->ctrl_base = (uint32_t) temp;
LOG_DEBUG("ASSUMING FESPI device at ctrl_base = 0x%x", fespi_info->ctrl_base); LOG_DEBUG("ASSUMING FESPI device at ctrl_base = 0x%x", fespi_info->ctrl_base);
} }
@ -1049,8 +1051,7 @@ static int fespi_probe(struct flash_bank *bank)
return ERROR_FAIL; return ERROR_FAIL;
} }
ctrl_base = target_device->ctrl_base; fespi_info->ctrl_base = target_device->ctrl_base;
fespi_info->ctrl_base = ctrl_base;
LOG_DEBUG("Valid FESPI on device %s at address 0x%" PRIx32, LOG_DEBUG("Valid FESPI on device %s at address 0x%" PRIx32,
target_device->name, bank->base); target_device->name, bank->base);
@ -1060,6 +1061,7 @@ static int fespi_probe(struct flash_bank *bank)
fespi_info->ctrl_base, fespi_info->ctrl_base,
bank->base); bank->base);
} }
ctrl_base = fespi_info->ctrl_base;
/* read and decode flash ID; returns in SW mode */ /* read and decode flash ID; returns in SW mode */
FESPI_WRITE_REG(FESPI_REG_TXCTRL, FESPI_TXWM(1)); FESPI_WRITE_REG(FESPI_REG_TXCTRL, FESPI_TXWM(1));

4
src/target/riscv/riscv.c
View File

@ -503,8 +503,8 @@ static int riscv_run_algorithm(struct target *target, int num_mem_params,
int64_t now = timeval_ms(); int64_t now = timeval_ms();
if (now - start > timeout_ms) { if (now - start > timeout_ms) {
LOG_ERROR("Algorithm timed out after %d ms.", timeout_ms); LOG_ERROR("Algorithm timed out after %d ms.", timeout_ms);
LOG_ERROR(" now = 0x%08x", now); LOG_ERROR(" now = 0x%08x", (uint32_t) now);
LOG_ERROR(" start = 0x%08x", start); LOG_ERROR(" start = 0x%08x", (uint32_t) start);
riscv_halt(target); riscv_halt(target);
riscv_openocd_poll(target); riscv_openocd_poll(target);
return ERROR_TARGET_TIMEOUT; return ERROR_TARGET_TIMEOUT;