Merge pull request #16 from sifive/0.13

Refactor code to support multiple debug spec versions.
__archive__
Tim Newsome 2017-02-06 09:20:15 -08:00 committed by GitHub
commit d78ee9303e
6 changed files with 5376 additions and 2298 deletions

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@ -136,6 +136,8 @@ INTEL_IA32_SRC = \
x86_32_common.c
RISCV_SRC = \
riscv/riscv-011.c \
riscv/riscv-013.c \
riscv/riscv.c
noinst_HEADERS = \

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@ -5,6 +5,13 @@
#define S0 8
#define S1 9
/*
* Disabling the warning we get when some opcodes functions aren't used. Not
* every user of this file uses every function, and it doesn't make sense to
* make them global. I suppose they could be macros.
*/
#pragma GCC diagnostic ignored "-Wunused-function"
static uint32_t bits(uint32_t value, unsigned int hi, unsigned int lo) {
return (value >> lo) & ((1 << (hi+1-lo)) - 1);
}

2605
src/target/riscv/riscv-011.c Normal file

File diff suppressed because it is too large Load Diff

2605
src/target/riscv/riscv-013.c Normal file

File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff

62
src/target/riscv/riscv.h Normal file
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@ -0,0 +1,62 @@
#ifndef RISCV_H
#define RISCV_H
#include "opcodes.h"
extern struct target_type riscv011_target;
extern struct target_type riscv013_target;
/*
* Definitions shared by code supporting all RISC-V versions.
*/
typedef struct {
unsigned dtm_version;
struct command_context *cmd_ctx;
void *version_specific;
/* Width of a GPR (and many other things) in bits. */
uint8_t xlen;
} riscv_info_t;
extern uint8_t ir_dtmcontrol[1];
extern struct scan_field select_dtmcontrol;
extern uint8_t ir_dbus[1];
extern struct scan_field select_dbus;
extern uint8_t ir_idcode[1];
extern struct scan_field select_idcode;
/*** Version-independent functions that we don't want in the main address space. ***/
static uint32_t load(const struct target *target, unsigned int rd,
unsigned int base, uint16_t offset)
{
riscv_info_t *info = (riscv_info_t *) target->arch_info;
switch (info->xlen) {
case 32:
return lw(rd, base, offset);
case 64:
return ld(rd, base, offset);
}
assert(0);
}
static uint32_t store(const struct target *target, unsigned int src,
unsigned int base, uint16_t offset)
{
riscv_info_t *info = (riscv_info_t *) target->arch_info;
switch (info->xlen) {
case 32:
return sw(src, base, offset);
case 64:
return sd(src, base, offset);
}
assert(0);
}
static unsigned xlen(const struct target *target)
{
riscv_info_t *info = (riscv_info_t *) target->arch_info;
return info->xlen;
}
#endif