David Brownell <david-b@pacbell.net>:
Update the Beagle setup:
- OMAP3530 updates:
* split ICEpick TAP enable support to its own file, for
reuse and eventually for storing other utility code
like emulation reset
* clean up, including labeling the tap as for DAP not
for the Cortex-A8 and making endianness non-variable
* add a few FIXMEs
- BeagleBoard cleanup: there's no SRST, "endstate" is gone, etc
I'm not sure I'd say it's further than "barely limping" just yet.
Key issues remain lack of Cortex-A8 support, and more complete
support for resetting.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2267 b42882b7-edfa-0310-969c-e2dbd0fdcd60
__archive__
zwelch
parent
7ddc6c3d55
commit
d727e31af9
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@ -1,14 +1,9 @@
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# OMAP3 BeagleBoard
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# http://beagleboard.org
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source [find target/omap3530.cfg]
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reset_config trst_and_srst
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jtag_reset 1 1
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sleep 10
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runtest 10
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jtag_reset 0 0
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# TI-14 JTAG connector
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reset_config trst_only
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endstate RUN/IDLE
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init
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omap3_dbginit
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# Later run: omap3_dbginit
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@ -0,0 +1,23 @@
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# Utilities for TI ICEpick-C ... used in DaVinci, OMAP3, and more.
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# jrc == TAP name for the ICEpick
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# port == a port number, 0..15
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proc icepick_c_tapenable {jrc port} {
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# NOTE: it's important not to enter RUN/IDLE state until
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# done sending these instructions and data to the ICEpick.
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# And never to enter RESET, which will disable the TAPs.
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# select router
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irscan $jrc 7 -endstate IRPAUSE
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drscan $jrc 8 0x89 -endstate DRPAUSE
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# set ip control
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irscan $jrc 2 -endstate IRPAUSE
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drscan $jrc 32 [expr 0xa0002108 + ($port << 24)] -endstate DRPAUSE
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irscan $jrc 0x3F -endstate RUN/IDLE
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runtest 10
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}
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# vim:syntax tcl
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@ -1,57 +1,68 @@
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#File omap3530.cfg - as found on the BEAGLEBOARD
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# Assumption is it is generic for all OMAP3530
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#TI OMAP3 processor - http://www.ti.com
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# TI OMAP3530
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# http://focus.ti.com/docs/prod/folders/print/omap3530.html
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# Other OMAP3 chips remove DSP and/or the OpenGL support
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME omap3
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set _CHIPNAME omap3530
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}
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if { [info exists ENDIAN] } {
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set _ENDIAN $ENDIAN
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} else {
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# this defaults to a little endianness
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set _ENDIAN little
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}
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# ICEpick-C ... used to route Cortex, DSP, and more not shown here
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source [find target/icepick.cfg]
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if { [info exists CPUTAPID ] } {
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set _CPUTAPID $CPUTAPID
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# Subsidiary TAP: C64x+ DSP ... must enable via ICEpick
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jtag newtap $_CHIPNAME dsp -irlen 38 -ircapture 0x25 -irmask 0x3f -disable
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# Subsidiary TAP: CoreSight Debug Access Port (DAP)
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if { [info exists DAP_TAPID ] } {
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set _DAP_TAPID $DAP_TAPID
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} else {
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# force an error till we get a good number
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set _CPUTAPID 0x0B6D602F
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set _DAP_TAPID 0x0b6d602f
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}
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jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf \
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-expected-id $_DAP_TAPID -disable
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jtag configure $_CHIPNAME.dap -event tap-enable \
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"icepick_c_tapenable $_CHIPNAME.jrc 3"
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#jtag scan chain
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jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0 -expected-id $_CPUTAPID -disable
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jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0xf -expected-id 0x0b7ae02f
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target create omap3.cpu cortex_m3 -endian little -chain-position omap3.cpu
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jtag configure $_CHIPNAME.cpu -event tap-enable {
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puts "Enabling Cortex-A8 @ OMAP3"
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irscan omap3.jrc 7 -endstate IRPAUSE
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drscan omap3.jrc 8 0x89 -endstate DRPAUSE
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irscan omap3.jrc 2 -endstate IRPAUSE
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drscan omap3.jrc 32 0xa3002108 -endstate RUN/IDLE
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irscan omap3.jrc 0x3F -endstate RUN/IDLE
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runtest 10
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puts "Cortex-A8 @ OMAP3 enabled"
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# Primary TAP: ICEpick-C (JTAG route controller) and boundary scan
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if { [info exists JRC_TAPID ] } {
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set _JRC_TAPID $JRC_TAPID
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} else {
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set _JRC_TAPID 0x0b7ae02f
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}
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jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
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-expected-id $_JRC_TAPID
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# GDB target: Cortex-A8, using DAP
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# FIXME when we have A8 support, use it. A8 != M3 ...
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target create omap3.cpu cortex_m3 -chain-position $_CHIPNAME.dap
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# FIXME much of this should be in reset event handlers
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proc omap3_dbginit { } {
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version
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jtag tapenable omap3.cpu
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reset
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sleep 500
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jtag tapenable omap3530.dap
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targets
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# sleep 1000
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# dap apsel 1
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# sleep 1000
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# dap apsel 1
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# dap info 1
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omap3.cpu mww 0x54011FB0 0xC5ACCE55 4
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# 0xd401.0000 - ETM
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# 0xd401.1000 - Cortex-A8
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# 0xd401.9000 - TPIU (traceport)
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# 0xd401.b000 - ETB
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# 0xd401.d000 - DAPCTL
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omap3.cpu mww 0x54011FB0 0xC5ACCE55
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omap3.cpu mdw 0x54011314
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omap3.cpu mdw 0x54011314
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# omap3.cpu mdw 0x54011080
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omap3.cpu mww 0x5401d030 0x00002000 4
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omap3.cpu mww 0x5401d030 0x00002000
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}
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