ARM11: don't expose DSCR
Remove the remaining extra copy of DSCR, and the register cache of which it was a part. That cache wasn't a very safe, or even necessary, idea; it was essentialy letting debugger-private state be manipulated by Tcl code that couldn't know how to do it right. This makes the "reg" output of an ARM11 resemble what most other ARM cores produce ... forward motion in the "make ARM11 work like the rest of the ARM cores" Jihad!__archive__
David Brownell
parent
f0c3e7011f
commit
d5e4e23f9a
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@ -46,41 +46,8 @@ static uint32_t arm11_vcr = 0;
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static bool arm11_config_step_irq_enable = false;
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static bool arm11_config_hardware_step = false;
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enum arm11_regtype
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{
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/* debug regs */
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ARM11_REGISTER_DSCR,
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};
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struct arm11_reg_defs
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{
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char * name;
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uint32_t num;
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int gdb_num;
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enum arm11_regtype type;
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};
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/* update arm11_regcache_ids when changing this */
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static const struct arm11_reg_defs arm11_reg_defs[] =
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{
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/* Debug Registers */
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{"dscr", 0, -1, ARM11_REGISTER_DSCR},
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};
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enum arm11_regcache_ids
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{
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ARM11_RC_DSCR,
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ARM11_RC_MAX,
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};
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static int arm11_step(struct target *target, int current,
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uint32_t address, int handle_breakpoints);
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/* helpers */
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static int arm11_build_reg_cache(struct target *target);
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static int arm11_set_reg(struct reg *reg, uint8_t *buf);
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static int arm11_get_reg(struct reg *reg);
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/** Check and if necessary take control of the system
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@ -127,11 +94,6 @@ static int arm11_check_init(struct arm11_common *arm11)
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return ERROR_OK;
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}
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#define R(x) \
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(arm11->reg_values[ARM11_RC_##x])
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/**
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* Save processor state. This is called after a HALT instruction
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* succeeds, and on other occasions the processor enters debug mode
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@ -148,17 +110,8 @@ static int arm11_debug_entry(struct arm11_common *arm11)
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/* REVISIT entire cache should already be invalid !!! */
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register_cache_invalidate(arm11->arm.core_cache);
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for (size_t i = 0; i < ARRAY_SIZE(arm11->reg_values); i++)
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{
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arm11->reg_list[i].valid = 1;
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arm11->reg_list[i].dirty = 0;
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}
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/* See e.g. ARM1136 TRM, "14.8.4 Entering Debug state" */
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/* Save DSCR */
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R(DSCR) = arm11->dscr;
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/* maybe save wDTR (pending DCC write to debug SW, e.g. libdcc) */
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arm11->is_wdtr_saved = !!(arm11->dscr & ARM11_DSCR_WDTR_FULL);
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if (arm11->is_wdtr_saved)
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@ -336,11 +289,9 @@ static int arm11_leave_debug_state(struct arm11_common *arm11, bool bpwp)
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register_cache_invalidate(arm11->arm.core_cache);
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/* restore DSCR */
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arm11_write_DSCR(arm11, R(DSCR));
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arm11_write_DSCR(arm11, arm11->dscr);
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/* maybe restore rDTR */
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if (arm11->is_rdtr_saved)
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{
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arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
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@ -722,9 +673,10 @@ static int arm11_step(struct target *target, int current,
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if (arm11_config_step_irq_enable)
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R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE; /* should be redundant */
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/* this disable should be redundant ... */
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arm11->dscr &= ~ARM11_DSCR_INTERRUPTS_DISABLE;
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else
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R(DSCR) |= ARM11_DSCR_INTERRUPTS_DISABLE;
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arm11->dscr |= ARM11_DSCR_INTERRUPTS_DISABLE;
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CHECK_RETVAL(arm11_leave_debug_state(arm11, handle_breakpoints));
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@ -769,8 +721,8 @@ static int arm11_step(struct target *target, int current,
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/* save state */
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CHECK_RETVAL(arm11_debug_entry(arm11));
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/* restore default state */
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R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE;
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/* restore default state */
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arm11->dscr &= ~ARM11_DSCR_INTERRUPTS_DISABLE;
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}
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@ -1199,12 +1151,7 @@ static int arm11_init_target(struct command_context *cmd_ctx,
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struct target *target)
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{
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/* Initialize anything we can set up without talking to the target */
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/* REVISIT do we really want such a debug-registers-only cache?
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* If we do, it should probably be handled purely by the DPM code,
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* so it works identically on the v7a/v7r cores.
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*/
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return arm11_build_reg_cache(target);
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return ERROR_OK;
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}
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/* talk to the target and set things up */
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@ -1309,117 +1256,6 @@ static int arm11_examine(struct target *target)
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}
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/** Load a register that is marked !valid in the register cache */
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static int arm11_get_reg(struct reg *reg)
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{
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struct arm11_reg_state *r = reg->arch_info;
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struct target *target = r->target;
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if (target->state != TARGET_HALTED)
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{
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LOG_WARNING("target was not halted");
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return ERROR_TARGET_NOT_HALTED;
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}
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/** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */
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#if 0
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struct arm11_common *arm11 = target_to_arm11(target);
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const struct arm11_reg_defs *arm11_reg_info = arm11_reg_defs + ((struct arm11_reg_state *)reg->arch_info)->def_index;
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#endif
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return ERROR_OK;
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}
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/** Change a value in the register cache */
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static int arm11_set_reg(struct reg *reg, uint8_t *buf)
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{
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struct arm11_reg_state *r = reg->arch_info;
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struct target *target = r->target;
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struct arm11_common *arm11 = target_to_arm11(target);
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// const struct arm11_reg_defs *arm11_reg_info = arm11_reg_defs + ((struct arm11_reg_state *)reg->arch_info)->def_index;
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arm11->reg_values[((struct arm11_reg_state *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32);
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reg->valid = 1;
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reg->dirty = 1;
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return ERROR_OK;
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}
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static const struct reg_arch_type arm11_reg_type = {
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.get = arm11_get_reg,
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.set = arm11_set_reg,
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};
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static int arm11_build_reg_cache(struct target *target)
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{
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struct arm11_common *arm11 = target_to_arm11(target);
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struct reg_cache *cache;
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struct reg *reg_list;
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struct arm11_reg_state *arm11_reg_states;
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cache = calloc(1, sizeof *cache);
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reg_list = calloc(ARM11_REGCACHE_COUNT, sizeof *reg_list);
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arm11_reg_states = calloc(ARM11_REGCACHE_COUNT,
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sizeof *arm11_reg_states);
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if (!cache || !reg_list || !arm11_reg_states) {
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free(cache);
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free(reg_list);
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free(arm11_reg_states);
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return ERROR_FAIL;
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}
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arm11->reg_list = reg_list;
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/* build cache for some of the debug registers */
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cache->name = "arm11 debug registers";
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cache->reg_list = reg_list;
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cache->num_regs = ARM11_REGCACHE_COUNT;
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struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
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(*cache_p) = cache;
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arm11->core_cache = cache;
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size_t i;
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/* Not very elegant assertion */
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if (ARM11_REGCACHE_COUNT != ARRAY_SIZE(arm11->reg_values) ||
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ARM11_REGCACHE_COUNT != ARRAY_SIZE(arm11_reg_defs) ||
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ARM11_REGCACHE_COUNT != ARM11_RC_MAX)
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{
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LOG_ERROR("BUG: arm11->reg_values inconsistent (%d %u %u %d)",
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ARM11_REGCACHE_COUNT,
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(unsigned) ARRAY_SIZE(arm11->reg_values),
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(unsigned) ARRAY_SIZE(arm11_reg_defs),
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ARM11_RC_MAX);
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/* FIXME minimally, use a build_bug_on(X) mechanism;
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* runtime exit() here is bad!
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*/
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exit(-1);
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}
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for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
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{
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struct reg * r = reg_list + i;
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const struct arm11_reg_defs * rd = arm11_reg_defs + i;
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struct arm11_reg_state * rs = arm11_reg_states + i;
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r->name = rd->name;
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r->size = 32;
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r->value = (uint8_t *)(arm11->reg_values + i);
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r->dirty = 0;
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r->valid = 0;
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r->type = &arm11_reg_type;
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r->arch_info = rs;
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rs->def_index = i;
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rs->target = target;
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}
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return ERROR_OK;
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}
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/* FIXME all these BOOL_WRAPPER things should be modifying
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* per-instance state, not shared state; ditto the vector
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* catch register support. Scan chains with multiple cores
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@ -26,8 +26,6 @@
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#include "armv4_5.h"
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#include "arm_dpm.h"
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#define ARM11_REGCACHE_COUNT 1
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#define ARM11_TAP_DEFAULT TAP_INVALID
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#define CHECK_RETVAL(action) \
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@ -69,18 +67,6 @@ struct arm11_common
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bool simulate_reset_on_next_halt; /**< Perform cleanups of the ARM state on next halt */
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/** \name Shadow registers to save debug state */
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/*@{*/
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struct reg * reg_list; /**< target register list */
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uint32_t reg_values[ARM11_REGCACHE_COUNT]; /**< data for registers */
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/*@}*/
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// GA
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struct reg_cache *core_cache;
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struct arm_jtag jtag_info;
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};
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