CortexA8: Introduce Freescale i.MX51 variant

This patch introduces support for Cortex A8 based Freescale i.MX51 CPU. This CPU
has the Debug Access Port located at a different address (0x60008000) than TI
OMAP3 series of CPUs.

i.MX51 configuration file based on OMAP3 configuration file and an email from
Alan Carvalho de Assis <acassis@gmail.com>.

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
__archive__
Marek Vasut 2010-10-29 02:57:32 +02:00
parent 1fa91f336a
commit d5b9c7998c
1 changed files with 51 additions and 0 deletions

51
tcl/target/imx51.cfg Normal file
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@ -0,0 +1,51 @@
# Freescale i.MX51
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME imx51
}
# CoreSight Debug Access Port
if { [info exists DAP_TAPID ] } {
set _DAP_TAPID $DAP_TAPID
} else {
set _DAP_TAPID 0x1ba00477
}
jtag newtap $_CHIPNAME DAP -irlen 4 -ircapture 0x1 -irmask 0xf \
-expected-id $_DAP_TAPID
# SDMA / no IDCODE
jtag newtap $_CHIPNAME SDMA -irlen 4 -ircapture 0x0 -irmask 0xf
# SJC
if { [info exists SJC_TAPID ] } {
set _SJC_TAPID SJC_TAPID
} else {
set _SJC_TAPID 0x0190c01d
}
jtag newtap $_CHIPNAME SJC -irlen 5 -ircapture 0x1 -irmask 0x1f \
-expected-id $_SJC_TAPID -ignore-version
# GDB target: Cortex-A8, using DAP
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.DAP
# some TCK tycles are required to activate the DEBUG power domain
jtag configure $_CHIPNAME.SJC -event post-reset "runtest 100"
# have the DAP "always" be active
jtag configure $_CHIPNAME.SJC -event setup "jtag tapenable $_CHIPNAME.DAP"
proc imx51_dbginit {target} {
# General Cortex A8 debug initialisation
cortex_a8 dbginit
}
# Slow speed to be sure it will work
jtag_rclk 1000
$_TARGETNAME configure -event "reset-start" { jtag_rclk 1000 }
$_TARGETNAME configure -event reset-assert-post "imx51_dbginit $_TARGETNAME"