stellaris: comments

Someday revisit various issues:  Tempest parts support writing
more than one word at a time; for some target firmware it might
be necessary to save and restore flash IRQ configuration.  (The
safest policy is likely to always reset after flash updates.)

Plus swap some undesirable TAB characters with SPACE.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
__archive__
David Brownell 2009-12-16 14:17:31 -08:00
parent 1cd7b3b49b
commit d265c219b9
2 changed files with 33 additions and 11 deletions

View File

@ -553,6 +553,11 @@ static int stellaris_read_part_info(struct flash_bank *bank)
stellaris_info->pagesize = 1024;
stellaris_info->pages_in_lockregion = 2;
/* REVISIT for at least Tempest parts, read NVMSTAT.FWB too.
* That exposes a 32-word Flash Write Buffer ... enabling
* writes of more than one word at a time.
*/
return ERROR_OK;
}
@ -640,6 +645,10 @@ static int stellaris_erase(struct flash_bank *bank, int first, int last)
target_write_u32(target, FLASH_CIM, 0);
target_write_u32(target, FLASH_MISC, PMISC | AMISC);
/* REVISIT this clobbers state set by any halted firmware ...
* it might want to process those IRQs.
*/
for (banknr = first; banknr <= last; banknr++)
{
/* Address is first word in page */
@ -726,6 +735,10 @@ static int stellaris_protect(struct flash_bank *bank, int set, int first, int la
target_write_u32(target, FLASH_CIM, 0);
target_write_u32(target, FLASH_MISC, PMISC | AMISC);
/* REVISIT this clobbers state set by any halted firmware ...
* it might want to process those IRQs.
*/
LOG_DEBUG("fmppe 0x%" PRIx32 "",fmppe);
target_write_u32(target, SCB_BASE | FMPPE, fmppe);
@ -921,6 +934,10 @@ static int stellaris_write(struct flash_bank *bank, uint8_t *buffer, uint32_t of
target_write_u32(target, FLASH_CIM, 0);
target_write_u32(target, FLASH_MISC, PMISC | AMISC);
/* REVISIT this clobbers state set by any halted firmware ...
* it might want to process those IRQs.
*/
/* multiple words to be programmed? */
if (words_remaining > 0)
{
@ -1068,6 +1085,10 @@ static int stellaris_mass_erase(struct flash_bank *bank)
target_write_u32(target, FLASH_CIM, 0);
target_write_u32(target, FLASH_MISC, PMISC | AMISC);
/* REVISIT this clobbers state set by any halted firmware ...
* it might want to process those IRQs.
*/
target_write_u32(target, FLASH_FMA, 0);
target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_MERASE);
/* Wait until erase complete */

View File

@ -53,18 +53,19 @@ struct stellaris_flash_bank
/* STELLARIS control registers */
#define SCB_BASE 0x400FE000
#define DID0 0x000
#define DID1 0x004
#define DC0 0x008
#define DC1 0x010
#define DC2 0x014
#define DC3 0x018
#define DC4 0x01C
#define DID0 0x000
#define DID1 0x004
#define DC0 0x008
#define DC1 0x010
#define DC2 0x014
#define DC3 0x018
#define DC4 0x01C
#define RIS 0x050
#define RCC 0x060
#define PLLCFG 0x064
#define RCC2 0x070
#define RIS 0x050
#define RCC 0x060
#define PLLCFG 0x064
#define RCC2 0x070
#define NVMSTAT 0x1a0
/* "legacy" flash memory protection registers (64KB max) */
#define FMPRE 0x130