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lpc1768: even if rclk "works", it isn't necessarily the correct clk 

rclk = 4MHz oon lpc1768, the correct JTAG clk is 666MHz(4MHz/6).

Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
__archive__
Øyvind Harboe 2010-08-02 13:21:21 +02:00
parent 6ed9ab5b58
commit d1638abd6a
1 changed files with 6 additions and 2 deletions
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8
tcl/target/lpc1768.cfg
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@ -50,8 +50,12 @@ flash bank $_FLASHNAME lpc2000 0x0 0x80000 0 0 $_TARGETNAME \
# JTAG clock should be CCLK/6 (unless using adaptive clocking) # JTAG clock should be CCLK/6 (unless using adaptive clocking)
# CCLK is 4 MHz after reset, and until board-specific code (like # CCLK is 4 MHz after reset, and until board-specific code (like
# a reset-init handler) speeds it up. # a reset-init handler) speeds it up.
jtag_rclk [ expr 4000 / 6 ] #
$_TARGETNAME configure -event reset-start { jtag_rclk [ expr 4000 / 6] } # Although rclk "appears to work", it turns out that this yields
# 4MHz whereas the "correct" rate is CCLK/6, which is not what
# you get with rclk.
jtag_khz [ expr 4000 / 6 ]
$_TARGETNAME configure -event reset-init { $_TARGETNAME configure -event reset-init {