aarch64: add symbolic definitions for armv8 opcodes
To replace hexadecimal constants with descriptive names and increase flexibility. Change-Id: I6f7b6f045866ed8b9360f54b640ecdb307eebc51 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>gitignore-build
Matthias Welwarsky
parent
6b554b3b0e
commit
ced4108d26
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@ -155,6 +155,7 @@ INTEL_IA32_SRC = \
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%D%/armv7m.h \
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%D%/armv7m_trace.h \
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%D%/armv8.h \
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%D%/armv8_opcodes.h \
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%D%/avrt.h \
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%D%/dsp563xx.h \
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%D%/dsp563xx_once.h \
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@ -0,0 +1,126 @@
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/*
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* Copyright (C) 2015 by pierrr kuo
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* vichy.kuo@gmail.com
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef OPENOCD_TARGET_ARMV8_OPCODES_H
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#define OPENOCD_TARGET_ARMV8_OPCODES_H
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#include "arm_opcodes.h"
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/* ARM V8 Move from system register to general purpose register
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* R = 1: SPSR R = 0: CPSR
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* Rn: target register
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*/
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#define SYSTEM_CUREL 0b1100001000010010
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#define SYSTEM_CUREL_MASK 0xC0
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#define SYSTEM_CUREL_SHIFT 6
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#define SYSTEM_CUREL_EL0 0x0
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#define SYSTEM_CUREL_EL1 0x1
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#define SYSTEM_CUREL_EL2 0x2
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#define SYSTEM_CUREL_EL3 0x3
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#define SYSTEM_CUREL_NONCH 0xF
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#define SYSTEM_AARCH64 0x1
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#define SYSTEM_AAR64_MODE_EL0t 0x0
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#define SYSTEM_AAR64_MODE_EL1t 0x4
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#define SYSTEM_AAR64_MODE_EL1h 0x5
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#define SYSTEM_AAR64_MODE_EL2t 0x8
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#define SYSTEM_AAR64_MODE_EL2h 0x9
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#define SYSTEM_AAR64_MODE_EL3t 0xC
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#define SYSTEM_AAR64_MODE_EL3h 0xd
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#define SYSTEM_DAIF 0b1101101000010001
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#define SYSTEM_DAIF_MASK 0x3C0
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#define SYSTEM_DAIF_SHIFT 6
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#define SYSTEM_ELR_EL1 0b1100001000000001
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#define SYSTEM_ELR_EL2 0b1110001000000001
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#define SYSTEM_ELR_EL3 0b1111001000000001
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#define SYSTEM_FPCR 0b1101101000100000
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#define SYSTEM_FPSR 0b1101101000100001
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#define SYSTEM_DAIF 0b1101101000010001
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#define SYSTEM_NZCV 0b1101101000010000
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#define SYSTEM_SP_EL0 0b1100001000001000
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#define SYSTEM_SP_EL1 0b1110001000001000
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#define SYSTEM_SP_EL2 0b1111001000001000
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#define SYSTEM_SP_SEL 0b1100001000010000
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#define SYSTEM_SPSR_ABT 0b1110001000011001
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#define SYSTEM_SPSR_FIQ 0b1110001000011011
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#define SYSTEM_SPSR_IRQ 0b1110001000011000
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#define SYSTEM_SPSR_UND 0b1110001000011010
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#define SYSTEM_SPSR_EL1 0b1100001000000000
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#define SYSTEM_SPSR_EL2 0b1110001000000000
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#define SYSTEM_SPSR_EL3 0b1111001000000000
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#define SYSTEM_ISR_EL1 0b1100011000001000
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#define SYSTEM_DBG_DSPSR_EL0 0b1101101000101000
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#define SYSTEM_DBG_DLR_EL0 0b1101101000101001
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#define SYSTEM_DBG_DTRRX_EL0 0b1001100000101000
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#define SYSTEM_DBG_DTRTX_EL0 0b1001100000101000
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#define SYSTEM_DBG_DBGDTR_EL0 0b1001100000100000
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#define SYSTEM_CCSIDR 0b1100100000000000
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#define SYSTEM_CLIDR 0b1100100000000001
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#define SYSTEM_CSSELR 0b1101000000000000
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#define SYSTEM_CTYPE 0b1101100000000001
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#define SYSTEM_DCCISW 0b0100001111110010
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#define SYSTEM_DCCSW 0b0100001111010010
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#define SYSTEM_ICIVAU 0b0101101110101001
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#define SYSTEM_DCCVAU 0b0101101111011001
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#define SYSTEM_MPIDR 0b1100000000000101
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#define SYSTEM_TCR_EL1 0b1100000100000010
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#define SYSTEM_TCR_EL2 0b1110000100000010
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#define SYSTEM_TCR_EL3 0b1111000100000010
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#define SYSTEM_TTBR0_EL1 0b1100000100000000
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#define SYSTEM_TTBR0_EL2 0b1110000100000000
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#define SYSTEM_TTBR0_EL3 0b1111000100000000
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#define SYSTEM_TTBR1_EL1 0b1100000100000001
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#define ARMV8_MRS_DSPSR(Rt) (0xd53b4500 | (Rt))
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#define ARMV8_MSR_DSPSR(Rt) (0xd51b4500 | (Rt))
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#define ARMV8_MRS_DLR(Rt) (0xd53b4520 | (Rt))
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#define ARMV8_MSR_DLR(Rt) (0xd51b4520 | (Rt))
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/* T32 ITR format */
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#define T32_FMTITR(instr) (((instr & 0x0000FFFF) << 16) | ((instr & 0xFFFF0000) >> 16))
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#define ARMV8_DCPS1(IM) (0xd4a00001 | (((IM) & 0xFFFF) << 5))
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#define ARMV8_DCPS2(IM) (0xd4a00002 | (((IM) & 0xFFFF) << 5))
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#define ARMV8_DCPS3(IM) (0xd4a00003 | (((IM) & 0xFFFF) << 5))
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#define DSB_SY 0xd5033F9F
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#define ARMV8_MRS(System, Rt) (0xd5300000 | ((System) << 5) | (Rt))
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/* ARM V8 Move to system register. */
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#define ARMV8_MSR_GP(System, Rt) \
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(0xd5100000 | ((System) << 5) | (Rt))
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/* ARM V8 Move immediate to process state field. */
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#define ARMV8_MSR_IM(Op1, CRm, Op2) \
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(0xd500401f | ((Op1) << 16) | ((CRm) << 8) | ((Op2) << 5))
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#define ARMV8_BKPT(Im) (0xD4200000 | ((Im & 0xffff) << 5))
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#define ARMV8_MOVFSP_64(Rt) ((1 << 31) | 0x11000000 | (0x1f << 5) | (Rt))
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#define ARMV8_MOVTSP_64(Rt) ((1 << 31) | 0x11000000 | (Rt << 5) | (0x1F))
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#define ARMV8_MOVFSP_32(Rt) (0x11000000 | (0x1f << 5) | (Rt))
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#define ARMV8_MOVTSP_32(Rt) (0x11000000 | (Rt << 5) | (0x1F))
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#endif /* __ARM_OPCODES_H */
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