aarch64: enable aarch32 debugging with arm gdb
When a PE is in Aarch32 state and gdb asks for a target description, provide a register view compatible with the "org.gnu.gdb.arm.core" feature. Only current-mode registers are exported, banked registers are not visible. Change-Id: I99a85d94831cf597fe8cff6a0a1818ce0a33613b Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>gitignore-build
Matthias Welwarsky
parent
ba82230856
commit
ccb1199d49
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@ -590,6 +590,7 @@ static int aarch64_internal_restart(struct target *target, bool slave_pe)
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/* registers are now invalid */
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register_cache_invalidate(arm->core_cache);
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register_cache_invalidate(arm->core_cache->next);
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return ERROR_OK;
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}
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@ -1012,12 +1012,39 @@ static const struct {
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{ ARMV8_SPSR_EL3, "SPSR_EL3", 32, ARMV8_64_EL3H, REG_TYPE_UINT32, "banked", "net.sourceforge.openocd.banked" },
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};
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#define ARMV8_NUM_REGS ARRAY_SIZE(armv8_regs)
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static const struct {
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unsigned id;
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const char *name;
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unsigned bits;
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enum arm_mode mode;
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enum reg_type type;
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const char *group;
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const char *feature;
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} armv8_regs32[] = {
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{ ARMV8_R0, "r0", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
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{ ARMV8_R1, "r1", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
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{ ARMV8_R2, "r2", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
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{ ARMV8_R3, "r3", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
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{ ARMV8_R4, "r4", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
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{ ARMV8_R5, "r5", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
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{ ARMV8_R6, "r6", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
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{ ARMV8_R7, "r7", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
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{ ARMV8_R8, "r8", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
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{ ARMV8_R9, "r9", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
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{ ARMV8_R10, "r10", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
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{ ARMV8_R11, "r11", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
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{ ARMV8_R12, "r12", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
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{ ARMV8_R13, "sp", 32, ARM_MODE_ANY, REG_TYPE_DATA_PTR, "general", "org.gnu.gdb.arm.core" },
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{ ARMV8_R14, "lr", 32, ARM_MODE_ANY, REG_TYPE_CODE_PTR, "general", "org.gnu.gdb.arm.core" },
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{ ARMV8_PC, "pc", 32, ARM_MODE_ANY, REG_TYPE_CODE_PTR, "general", "org.gnu.gdb.arm.core" },
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{ ARMV8_xPSR, "cpsr", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
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};
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#define ARMV8_NUM_REGS ARRAY_SIZE(armv8_regs)
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#define ARMV8_NUM_REGS32 ARRAY_SIZE(armv8_regs32)
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static int armv8_get_core_reg(struct reg *reg)
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{
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int retval;
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struct arm_reg *armv8_reg = reg->arch_info;
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struct target *target = armv8_reg->target;
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struct arm *arm = target_to_arm(target);
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@ -1025,9 +1052,7 @@ static int armv8_get_core_reg(struct reg *reg)
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if (target->state != TARGET_HALTED)
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return ERROR_TARGET_NOT_HALTED;
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retval = arm->read_core_reg(target, reg, armv8_reg->num, arm->core_mode);
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return retval;
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return arm->read_core_reg(target, reg, armv8_reg->num, arm->core_mode);
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}
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static int armv8_set_core_reg(struct reg *reg, uint8_t *buf)
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@ -1057,25 +1082,83 @@ static const struct reg_arch_type armv8_reg_type = {
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.set = armv8_set_core_reg,
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};
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static int armv8_get_core_reg32(struct reg *reg)
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{
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struct arm_reg *armv8_reg = reg->arch_info;
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struct target *target = armv8_reg->target;
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struct arm *arm = target_to_arm(target);
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struct reg_cache *cache = arm->core_cache;
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struct reg *reg64;
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int retval;
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LOG_DEBUG("reg.name:%s number:%i arm.num:%i value:0x%08" PRIx64,
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reg->name, reg->number, armv8_reg->num, buf_get_u64(reg->value, 0, 32));
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/* get the corresponding Aarch64 register */
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reg64 = cache->reg_list + armv8_reg->num;
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if (reg64->valid) {
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reg->valid = true;
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return ERROR_OK;
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}
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retval = arm->read_core_reg(target, reg, armv8_reg->num, arm->core_mode);
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if (retval == ERROR_OK)
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reg->valid = reg64->valid;
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return retval;
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}
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static int armv8_set_core_reg32(struct reg *reg, uint8_t *buf)
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{
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struct arm_reg *armv8_reg = reg->arch_info;
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struct target *target = armv8_reg->target;
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struct arm *arm = target_to_arm(target);
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struct reg_cache *cache = arm->core_cache;
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struct reg *reg64 = cache->reg_list + armv8_reg->num;
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uint32_t value = buf_get_u32(buf, 0, 32);
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if (target->state != TARGET_HALTED)
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return ERROR_TARGET_NOT_HALTED;
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if (reg64 == arm->cpsr) {
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armv8_set_cpsr(arm, value);
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} else {
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buf_set_u32(reg->value, 0, 32, value);
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reg->valid = 1;
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reg64->valid = 1;
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}
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reg64->dirty = 1;
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return ERROR_OK;
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}
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static const struct reg_arch_type armv8_reg32_type = {
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.get = armv8_get_core_reg32,
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.set = armv8_set_core_reg32,
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};
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/** Builds cache of architecturally defined registers. */
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struct reg_cache *armv8_build_reg_cache(struct target *target)
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{
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struct armv8_common *armv8 = target_to_armv8(target);
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struct arm *arm = &armv8->arm;
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int num_regs = ARMV8_NUM_REGS;
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int num_regs32 = ARMV8_NUM_REGS32;
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struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
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struct reg_cache *cache = malloc(sizeof(struct reg_cache));
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struct reg_cache *cache32 = malloc(sizeof(struct reg_cache));
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struct reg *reg_list = calloc(num_regs, sizeof(struct reg));
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struct reg *reg_list32 = calloc(num_regs32, sizeof(struct reg));
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struct arm_reg *arch_info = calloc(num_regs, sizeof(struct arm_reg));
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struct reg_feature *feature;
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int i;
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/* Build the process context cache */
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cache->name = "arm v8 registers";
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cache->next = NULL;
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cache->name = "Aarch64 registers";
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cache->next = cache32;
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cache->reg_list = reg_list;
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cache->num_regs = num_regs;
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(*cache_p) = cache;
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for (i = 0; i < num_regs; i++) {
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arch_info[i].num = armv8_regs[i].id;
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@ -1086,8 +1169,6 @@ struct reg_cache *armv8_build_reg_cache(struct target *target)
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reg_list[i].name = armv8_regs[i].name;
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reg_list[i].size = armv8_regs[i].bits;
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reg_list[i].value = calloc(1, 8);
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reg_list[i].dirty = 0;
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reg_list[i].valid = 0;
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reg_list[i].type = &armv8_reg_type;
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reg_list[i].arch_info = &arch_info[i];
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@ -1114,6 +1195,38 @@ struct reg_cache *armv8_build_reg_cache(struct target *target)
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arm->pc = reg_list + ARMV8_PC;
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arm->core_cache = cache;
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/* shadow cache for ARM mode registers */
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cache32->name = "Aarch32 registers";
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cache32->next = NULL;
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cache32->reg_list = reg_list32;
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cache32->num_regs = num_regs32;
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for (i = 0; i < num_regs32; i++) {
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reg_list32[i].name = armv8_regs32[i].name;
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reg_list32[i].size = armv8_regs32[i].bits;
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reg_list32[i].value = &arch_info[armv8_regs32[i].id].value[0];
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reg_list32[i].type = &armv8_reg32_type;
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reg_list32[i].arch_info = &arch_info[armv8_regs32[i].id];
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reg_list32[i].group = armv8_regs32[i].group;
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reg_list32[i].number = i;
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reg_list32[i].exist = true;
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reg_list32[i].caller_save = true;
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feature = calloc(1, sizeof(struct reg_feature));
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if (feature) {
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feature->name = armv8_regs32[i].feature;
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reg_list32[i].feature = feature;
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} else
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LOG_ERROR("unable to allocate feature list");
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reg_list32[i].reg_data_type = calloc(1, sizeof(struct reg_data_type));
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if (reg_list32[i].reg_data_type)
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reg_list32[i].reg_data_type->type = armv8_regs32[i].type;
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else
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LOG_ERROR("unable to allocate reg type list");
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}
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(*cache_p) = cache;
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return cache;
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}
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@ -1143,27 +1256,50 @@ int armv8_get_gdb_reg_list(struct target *target,
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struct arm *arm = target_to_arm(target);
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int i;
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switch (reg_class) {
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case REG_CLASS_GENERAL:
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*reg_list_size = ARMV8_ELR_EL1;
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*reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
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if (arm->core_state == ARM_STATE_AARCH64) {
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for (i = 0; i < *reg_list_size; i++)
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(*reg_list)[i] = armv8_reg_current(arm, i);
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LOG_DEBUG("Creating Aarch64 register list");
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return ERROR_OK;
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case REG_CLASS_ALL:
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*reg_list_size = ARMV8_LAST_REG;
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*reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
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switch (reg_class) {
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case REG_CLASS_GENERAL:
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*reg_list_size = ARMV8_ELR_EL1;
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*reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
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for (i = 0; i < *reg_list_size; i++)
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(*reg_list)[i] = armv8_reg_current(arm, i);
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for (i = 0; i < *reg_list_size; i++)
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(*reg_list)[i] = armv8_reg_current(arm, i);
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return ERROR_OK;
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return ERROR_OK;
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case REG_CLASS_ALL:
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*reg_list_size = ARMV8_LAST_REG;
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*reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
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default:
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LOG_ERROR("not a valid register class type in query.");
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return ERROR_FAIL;
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break;
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for (i = 0; i < *reg_list_size; i++)
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(*reg_list)[i] = armv8_reg_current(arm, i);
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return ERROR_OK;
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default:
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LOG_ERROR("not a valid register class type in query.");
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return ERROR_FAIL;
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}
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} else {
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struct reg_cache *cache32 = arm->core_cache->next;
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LOG_DEBUG("Creating Aarch32 register list");
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switch (reg_class) {
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case REG_CLASS_GENERAL:
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case REG_CLASS_ALL:
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*reg_list_size = cache32->num_regs;
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*reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
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for (i = 0; i < *reg_list_size; i++)
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(*reg_list)[i] = cache32->reg_list + i;
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return ERROR_OK;
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default:
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LOG_ERROR("not a valid register class type in query.");
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return ERROR_FAIL;
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}
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}
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}
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