contrib: add source to the cfi flash loaders

Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>

contrib/loaders/flash/armv4_5_cfi_intel_16.s

@@ -0,0 +1,57 @@
+/***************************************************************************
+ *   Copyright (C) 2005, 2007 by Dominic Rath                              *
+ *   Dominic.Rath@gmx.de                                                   *
+ *   Copyright (C) 2010 Spencer Oliver                                     *
+ *   spen@spen-soft.co.uk                                                  *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ *                                                                         *
+ *   This program is distributed in the hope that it will be useful,       *
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
+ *   GNU General Public License for more details.                          *
+ *                                                                         *
+ *   You should have received a copy of the GNU General Public License     *
+ *   along with this program; if not, write to the                         *
+ *   Free Software Foundation, Inc.,                                       *
+ *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
+ ***************************************************************************/
+
+	.text
+	.arm
+	.arch armv4
+
+	.section .init
+
+/* algorithm register usage:
+ * r0: source address (in RAM)
+ * r1: target address (in Flash)
+ * r2: count
+ * r3: flash write command
+ * r4: status byte (returned to host)
+ * r5: busy test pattern
+ * r6: error test pattern
+ */
+
+loop:
+	ldrh	r4, [r0], #2
+	strh	r3, [r1]
+	strh	r4, [r1]
+busy:
+	ldrh	r4, [r1]
+	and		r7, r4, r5
+	cmp		r7, r5
+	bne		busy
+	tst		r4, r6
+	bne		done
+	subs	r2, r2, #1
+	beq		done
+	add		r1, r1, #2
+	b		loop
+done:
+	b		done
+
+	.end

contrib/loaders/flash/armv4_5_cfi_intel_32.s

@@ -0,0 +1,57 @@
+/***************************************************************************
+ *   Copyright (C) 2005, 2007 by Dominic Rath                              *
+ *   Dominic.Rath@gmx.de                                                   *
+ *   Copyright (C) 2010 Spencer Oliver                                     *
+ *   spen@spen-soft.co.uk                                                  *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ *                                                                         *
+ *   This program is distributed in the hope that it will be useful,       *
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
+ *   GNU General Public License for more details.                          *
+ *                                                                         *
+ *   You should have received a copy of the GNU General Public License     *
+ *   along with this program; if not, write to the                         *
+ *   Free Software Foundation, Inc.,                                       *
+ *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
+ ***************************************************************************/
+
+	.text
+	.arm
+	.arch armv4
+
+	.section .init
+
+/* algorithm register usage:
+ * r0: source address (in RAM)
+ * r1: target address (in Flash)
+ * r2: count
+ * r3: flash write command
+ * r4: status byte (returned to host)
+ * r5: busy test pattern
+ * r6: error test pattern
+ */
+
+loop:
+	ldr		r4, [r0], #4
+	str		r3, [r1]
+	str		r4, [r1]
+busy:
+	ldr		r4, [r1]
+	and		r7, r4, r5
+	cmp		r7, r5
+	bne		busy
+	tst		r4, r6
+	bne		done
+	subs	r2, r2, #1
+	beq		done
+	add		r1, r1, #4
+	b		loop
+done:
+	b		done
+
+	.end

contrib/loaders/flash/armv4_5_cfi_intel_8.s

@@ -0,0 +1,57 @@
+/***************************************************************************
+ *   Copyright (C) 2005, 2007 by Dominic Rath                              *
+ *   Dominic.Rath@gmx.de                                                   *
+ *   Copyright (C) 2010 Spencer Oliver                                     *
+ *   spen@spen-soft.co.uk                                                  *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ *                                                                         *
+ *   This program is distributed in the hope that it will be useful,       *
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
+ *   GNU General Public License for more details.                          *
+ *                                                                         *
+ *   You should have received a copy of the GNU General Public License     *
+ *   along with this program; if not, write to the                         *
+ *   Free Software Foundation, Inc.,                                       *
+ *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
+ ***************************************************************************/
+
+	.text
+	.arm
+	.arch armv4
+
+	.section .init
+
+/* algorithm register usage:
+ * r0: source address (in RAM)
+ * r1: target address (in Flash)
+ * r2: count
+ * r3: flash write command
+ * r4: status byte (returned to host)
+ * r5: busy test pattern
+ * r6: error test pattern
+ */
+
+loop:
+	ldrb	r4, [r0], #1
+	strb	r3, [r1]
+	strb	r4, [r1]
+busy:
+	ldrb	r4, [r1]
+	and		r7, r4, r5
+	cmp		r7, r5
+	bne		busy
+	tst		r4, r6
+	bne		done
+	subs	r2, r2, #1
+	beq		done
+	add		r1, r1, #1
+	b		loop
+done:
+	b		done
+
+	.end

contrib/loaders/flash/armv4_5_cfi_span_16.s

@@ -0,0 +1,75 @@
+/***************************************************************************
+ *   Copyright (C) 2005, 2007 by Dominic Rath                              *
+ *   Dominic.Rath@gmx.de                                                   *
+ *   Copyright (C) 2010 Spencer Oliver                                     *
+ *   spen@spen-soft.co.uk                                                  *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ *                                                                         *
+ *   This program is distributed in the hope that it will be useful,       *
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
+ *   GNU General Public License for more details.                          *
+ *                                                                         *
+ *   You should have received a copy of the GNU General Public License     *
+ *   along with this program; if not, write to the                         *
+ *   Free Software Foundation, Inc.,                                       *
+ *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
+ ***************************************************************************/
+
+	.text
+	.arm
+	.arch armv4
+
+	.section .init
+
+/* input parameters - */
+/*	R0 = source address */
+/*	R1 = destination address */
+/*	R2 = number of writes */
+/*	R3 = flash write command */
+/*	R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
+/* output parameters - */
+/*	R5 = 0x80 ok 0x00 bad */
+/* temp registers - */
+/*	R6 = value read from flash to test status */
+/*	R7 = holding register */
+/* unlock registers - */
+/*  R8 = unlock1_addr */
+/*  R9 = unlock1_cmd */
+/*  R10 = unlock2_addr */
+/*  R11 = unlock2_cmd */
+
+code:
+	ldrh	r5, [r0], #2
+	strh	r9, [r8]
+	strh	r11, [r10]
+	strh	r3, [r8]
+	strh	r5, [r1]
+	nop
+busy:
+	ldrh	r6, [r1]
+	eor		r7, r5, r6
+	ands	r7, r4, r7
+	beq		cont			/* b if DQ7 == Data7 */
+	ands	r6, r6, r4, lsr #2
+	beq		busy			/* b if DQ5 low */
+	ldrh	r6, [r1]
+	eor		r7, r5, r6
+	ands	r7, r4, r7
+	beq		cont			/* b if DQ7 == Data7 */
+	mov		r5, #0			/* 0x0 - return 0x00, error */
+	bne		done
+cont:
+	subs	r2, r2, #1		/* 0x1 */
+	moveq	r5, #128		/* 0x80 */
+	beq		done
+	add		r1, r1, #2		/* 0x2 */
+	b		code
+done:
+	b		done
+
+	.end

contrib/loaders/flash/armv4_5_cfi_span_16_dq7.s

@@ -0,0 +1,66 @@
+/***************************************************************************
+ *   Copyright (C) 2005, 2007 by Dominic Rath                              *
+ *   Dominic.Rath@gmx.de                                                   *
+ *   Copyright (C) 2010 Spencer Oliver                                     *
+ *   spen@spen-soft.co.uk                                                  *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ *                                                                         *
+ *   This program is distributed in the hope that it will be useful,       *
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
+ *   GNU General Public License for more details.                          *
+ *                                                                         *
+ *   You should have received a copy of the GNU General Public License     *
+ *   along with this program; if not, write to the                         *
+ *   Free Software Foundation, Inc.,                                       *
+ *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
+ ***************************************************************************/
+
+	.text
+	.arm
+	.arch armv4
+
+	.section .init
+
+/* input parameters - */
+/*	R0 = source address */
+/*	R1 = destination address */
+/*	R2 = number of writes */
+/*	R3 = flash write command */
+/*	R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
+/* output parameters - */
+/*	R5 = 0x80 ok 0x00 bad */
+/* temp registers - */
+/*	R6 = value read from flash to test status */
+/*	R7 = holding register */
+/* unlock registers - */
+/*  R8 = unlock1_addr */
+/*  R9 = unlock1_cmd */
+/*  R10 = unlock2_addr */
+/*  R11 = unlock2_cmd */
+
+code:
+	ldrh	r5, [r0], #2
+	strh	r9, [r8]
+	strh	r11, [r10]
+	strh	r3, [r8]
+	strh	r5, [r1]
+	nop
+busy:
+	ldrh	r6, [r1]
+	eor		r7, r5, r6
+	ands	r7, #0x80
+	bne		busy
+	subs	r2, r2, #1	/* 0x1 */
+	moveq	r5, #128	/* 0x80 */
+	beq		done
+	add		r1, r1, #2	/* 0x2 */
+	b		code
+done:
+	b		done
+
+	.end

contrib/loaders/flash/armv4_5_cfi_span_32.s

@@ -0,0 +1,75 @@
+/***************************************************************************
+ *   Copyright (C) 2005, 2007 by Dominic Rath                              *
+ *   Dominic.Rath@gmx.de                                                   *
+ *   Copyright (C) 2010 Spencer Oliver                                     *
+ *   spen@spen-soft.co.uk                                                  *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ *                                                                         *
+ *   This program is distributed in the hope that it will be useful,       *
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
+ *   GNU General Public License for more details.                          *
+ *                                                                         *
+ *   You should have received a copy of the GNU General Public License     *
+ *   along with this program; if not, write to the                         *
+ *   Free Software Foundation, Inc.,                                       *
+ *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
+ ***************************************************************************/
+
+	.text
+	.arm
+	.arch armv4
+
+	.section .init
+
+/* input parameters - */
+/*	R0 = source address */
+/*	R1 = destination address */
+/*	R2 = number of writes */
+/*	R3 = flash write command */
+/*	R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
+/* output parameters - */
+/*	R5 = 0x80 ok 0x00 bad */
+/* temp registers - */
+/*	R6 = value read from flash to test status */
+/*	R7 = holding register */
+/* unlock registers - */
+/*  R8 = unlock1_addr */
+/*  R9 = unlock1_cmd */
+/*  R10 = unlock2_addr */
+/*  R11 = unlock2_cmd */
+
+code:
+	ldr		r5, [r0], #4
+	str		r9, [r8]
+	str		r11, [r10]
+	str		r3, [r8]
+	str		r5, [r1]
+	nop
+busy:
+	ldr		r6, [r1]
+	eor		r7, r5, r6
+	ands	r7, r4, r7
+	beq		cont			/* b if DQ7 == Data7 */
+	ands	r6, r6, r4, lsr #2
+	beq		busy			/* b if DQ5 low */
+	ldr		r6, [r1]
+	eor		r7, r5, r6
+	ands	r7, r4, r7
+	beq		cont			/* b if DQ7 == Data7 */
+	mov		r5, #0			/* 0x0 - return 0x00, error */
+	bne		done
+cont:
+	subs	r2, r2, #1		/* 0x1 */
+	moveq	r5, #128		/* 0x80 */
+	beq		done
+	add		r1, r1, #4		/* 0x4 */
+	b		code
+done:
+	b		done
+
+	.end

contrib/loaders/flash/armv4_5_cfi_span_8.s

@@ -0,0 +1,75 @@
+/***************************************************************************
+ *   Copyright (C) 2005, 2007 by Dominic Rath                              *
+ *   Dominic.Rath@gmx.de                                                   *
+ *   Copyright (C) 2010 Spencer Oliver                                     *
+ *   spen@spen-soft.co.uk                                                  *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ *                                                                         *
+ *   This program is distributed in the hope that it will be useful,       *
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
+ *   GNU General Public License for more details.                          *
+ *                                                                         *
+ *   You should have received a copy of the GNU General Public License     *
+ *   along with this program; if not, write to the                         *
+ *   Free Software Foundation, Inc.,                                       *
+ *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
+ ***************************************************************************/
+
+	.text
+	.arm
+	.arch armv4
+	
+	.section .init
+
+/* input parameters - */
+/*	R0 = source address */
+/*	R1 = destination address */
+/*	R2 = number of writes */
+/*	R3 = flash write command */
+/*	R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
+/* output parameters - */
+/*	R5 = 0x80 ok 0x00 bad */
+/* temp registers - */
+/*	R6 = value read from flash to test status */
+/*	R7 = holding register */
+/* unlock registers - */
+/*  R8 = unlock1_addr */
+/*  R9 = unlock1_cmd */
+/*  R10 = unlock2_addr */
+/*  R11 = unlock2_cmd */
+
+code:
+	ldrb	r5, [r0], #1
+	strb	r9, [r8]
+	strb	r11, [r10]
+	strb	r3, [r8]
+	strb	r5, [r1]
+	nop
+busy:
+	ldrb	r6, [r1]
+	eor		r7, r5, r6
+	ands	r7, r4, r7
+	beq		cont			/* b if DQ7 == Data7 */
+	ands	r6, r6, r4, lsr #2
+	beq		busy			/* b if DQ5 low */
+	ldrb	r6, [r1]
+	eor		r7, r5, r6
+	ands	r7, r4, r7
+	beq		cont			/* b if DQ7 == Data7 */
+	mov		r5, #0			/* 0x0 - return 0x00, error */
+	bne		done
+cont:
+	subs	r2, r2, #1		/* 0x1 */
+	moveq	r5, #128		/* 0x80 */
+	beq		done
+	add		r1, r1, #1		/* 0x1 */
+	b		code
+done:
+	b		done
+
+	.end

src/flash/nor/cfi.c

@@ -1226,6 +1226,7 @@ static int cfi_intel_write_block(struct flash_bank *bank, uint8_t *buffer,
 	 * r6: error test pattern
 	 */
 
+	/* see contib/loaders/flash/armv4_5_cfi_intel_32.s for src */
 	static const uint32_t word_32_code[] = {
 		0xe4904004,   /* loop:	ldr r4, [r0], #4 */
 		0xe5813000,   /* 		str r3, [r1] */
@@ -1243,6 +1244,7 @@ static int cfi_intel_write_block(struct flash_bank *bank, uint8_t *buffer,
 		0xeafffffe    /* done:	b -2 */
 	};
 
+	/* see contib/loaders/flash/armv4_5_cfi_intel_16.s for src */
 	static const uint32_t word_16_code[] = {
 		0xe0d040b2,   /* loop:	ldrh r4, [r0], #2 */
 		0xe1c130b0,   /* 		strh r3, [r1] */
@@ -1260,6 +1262,7 @@ static int cfi_intel_write_block(struct flash_bank *bank, uint8_t *buffer,
 		0xeafffffe    /* done:	b -2 */
 	};
 
+	/* see contib/loaders/flash/armv4_5_cfi_intel_8.s for src */
 	static const uint32_t word_8_code[] = {
 		0xe4d04001,   /* loop:	ldrb r4, [r0], #1 */
 		0xe5c13000,   /* 		strb r3, [r1] */
@@ -1487,6 +1490,7 @@ static int cfi_spansion_write_block(struct flash_bank *bank, uint8_t *buffer,
 	/*  R10 = unlock2_addr */
 	/*  R11 = unlock2_cmd */
 
+	/* see contib/loaders/flash/armv4_5_cfi_span_32.s for src */
 	static const uint32_t word_32_code[] = {
 						/* 00008100 <sp_32_code>:		*/
 		0xe4905004,		/* ldr	r5, [r0], #4			*/
@@ -1519,9 +1523,10 @@ static int cfi_spansion_write_block(struct flash_bank *bank, uint8_t *buffer,
 						/*								*/
 						/* 00008154 <sp_32_done>:		*/
 		0xeafffffe		/* b	8154 <sp_32_done>		*/
-		};
+	};
 
-		static const uint32_t word_16_code[] = {
+	/* see contib/loaders/flash/armv4_5_cfi_span_16.s for src */
+	static const uint32_t word_16_code[] = {
 						/* 00008158 <sp_16_code>:		*/
 		0xe0d050b2,		/* ldrh	r5, [r0], #2			*/
 		0xe1c890b0,		/* strh	r9, [r8]				*/
@@ -1553,9 +1558,10 @@ static int cfi_spansion_write_block(struct flash_bank *bank, uint8_t *buffer,
 						/* 								*/
 						/* 000081ac <sp_16_done>:		*/
 		0xeafffffe		/* b	81ac <sp_16_done>		*/
-		};
+	};
 
-		static const uint32_t word_16_code_dq7only[] = {
+	/* see contib/loaders/flash/armv4_5_cfi_span_16_dq7.s for src */
+	static const uint32_t word_16_code_dq7only[] = {
 						/* <sp_16_code>:				*/
 		0xe0d050b2,		/* ldrh r5, [r0], #2			*/
 		0xe1c890b0,		/* strh r9, [r8]				*/
@@ -1578,9 +1584,10 @@ static int cfi_spansion_write_block(struct flash_bank *bank, uint8_t *buffer,
 						/* 								*/
 						/* 000081ac <sp_16_done>:		*/
 		0xeafffffe		/* b	81ac <sp_16_done>		*/
-		};
+	};
 
-		static const uint32_t word_8_code[] = {
+	/* see contib/loaders/flash/armv4_5_cfi_span_8.s for src */
+	static const uint32_t word_8_code[] = {
 						/* 000081b0 <sp_16_code_end>:	*/
 		0xe4d05001,		/* ldrb	r5, [r0], #1			*/
 		0xe5c89000,		/* strb	r9, [r8]				*/