zcy
/
tinyriscv-openocd
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

arm11: initialise DPM and register cache before reading DSCR for the first time 

When target was already halted during the initial examination,
arm11_check_init() was trying to read, store and interpret DSCR
contents before the DPM structure is initialised. This caused
a segfault like described on
http://sourceforge.net/apps/trac/openocd/ticket/65 .

This is a totally untested attempt to fix this issue.

Change-Id: I2fff115679a3f0023e7a88c749ccb5f045d6cf01
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2043
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
__archive__
Paul Fertser 2014-03-13 13:27:45 +04:00
parent d019080dfa
commit ca0e237d39
1 changed files with 6 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
src/target/arm11.c
View File

@ -1177,6 +1177,12 @@ static int arm11_examine(struct target *target)
LOG_DEBUG("IDCODE %08" PRIx32 " IMPLEMENTOR %02x DIDR %08" PRIx32,
device_id, implementor, didr);
/* Build register cache "late", after target_init(), since we
* want to know if this core supports Secure Monitor mode.
*/
if (!target_was_examined(target))
CHECK_RETVAL(arm11_dpm_init(arm11, didr));
/* as a side-effect this reads DSCR and thus
* clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
* as suggested by the spec.
@ -1186,12 +1192,6 @@ static int arm11_examine(struct target *target)
if (retval != ERROR_OK)
return retval;
/* Build register cache "late", after target_init(), since we
* want to know if this core supports Secure Monitor mode.
*/
if (!target_was_examined(target))
CHECK_RETVAL(arm11_dpm_init(arm11, didr));
/* ETM on ARM11 still uses original scanchain 6 access mode */
if (arm11->arm.etm && !target_was_examined(target)) {
*register_get_last_cache_p(&target->reg_cache) =