- disabled use of single-step bit for EmbeddedICE version 6 cores
git-svn-id: svn://svn.berlios.de/openocd/trunk@128 b42882b7-edfa-0310-969c-e2dbd0fdcd60__archive__
parent
30ebf9fece
commit
c7383a8bea
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@ -18,7 +18,7 @@
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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#define OPENOCD_VERSION "Open On-Chip Debugger (2006-01-25 11:30 CET)"
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#define OPENOCD_VERSION "Open On-Chip Debugger (2006-01-26 13:30 CET)"
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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@ -169,7 +169,6 @@ reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7
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case 6:
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reg_list[EICE_DBG_CTRL].size = 6;
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reg_list[EICE_DBG_STAT].size = 10;
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arm7_9->has_single_step = 1;
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arm7_9->has_monitor_mode = 1;
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break;
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default:
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