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Change tap_state naming to be consistent with SVF documentation. 

Courtesy of Dick Hollenbeck <dick@softplc.com>


git-svn-id: svn://svn.berlios.de/openocd/trunk@1232 b42882b7-edfa-0310-969c-e2dbd0fdcd60
__archive__
kc8apf 2008-12-13 06:25:50 +00:00
parent 6c27550f6e
commit c45de8073d
30 changed files with 1463 additions and 1468 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

54
src/flash/str9xpec.c
View File

@ -145,7 +145,7 @@ u8 str9xpec_isc_status(jtag_tap_t *tap)
scan_field_t field;
u8 status;
if (str9xpec_set_instr(tap, ISC_NOOP, TAP_PI) != ERROR_OK)
if (str9xpec_set_instr(tap, ISC_NOOP, TAP_IRPAUSE) != ERROR_OK)
return ISC_STATUS_ERROR;
field.tap = tap;
@ -158,7 +158,7 @@ u8 str9xpec_isc_status(jtag_tap_t *tap)
field.in_handler = NULL;
field.in_handler_priv = NULL;
jtag_add_dr_scan(1, &field, TAP_RTI);
jtag_add_dr_scan(1, &field, TAP_IDLE);
jtag_execute_queue();
LOG_DEBUG("status: 0x%2.2x", status);
@ -181,7 +181,7 @@ int str9xpec_isc_enable(struct flash_bank_s *bank)
return ERROR_OK;
/* enter isc mode */
if (str9xpec_set_instr(tap, ISC_ENABLE, TAP_RTI) != ERROR_OK)
if (str9xpec_set_instr(tap, ISC_ENABLE, TAP_IDLE) != ERROR_OK)
return ERROR_TARGET_INVALID;
/* check ISC status */
@ -207,7 +207,7 @@ int str9xpec_isc_disable(struct flash_bank_s *bank)
if (!str9xpec_info->isc_enable)
return ERROR_OK;
if (str9xpec_set_instr(tap, ISC_DISABLE, TAP_RTI) != ERROR_OK)
if (str9xpec_set_instr(tap, ISC_DISABLE, TAP_IDLE) != ERROR_OK)
return ERROR_TARGET_INVALID;
/* delay to handle aborts */
@ -238,7 +238,7 @@ int str9xpec_read_config(struct flash_bank_s *bank)
LOG_DEBUG("ISC_CONFIGURATION");
/* execute ISC_CONFIGURATION command */
str9xpec_set_instr(tap, ISC_CONFIGURATION, TAP_PI);
str9xpec_set_instr(tap, ISC_CONFIGURATION, TAP_IRPAUSE);
field.tap = tap;
field.num_bits = 64;
@ -250,7 +250,7 @@ int str9xpec_read_config(struct flash_bank_s *bank)
field.in_handler = NULL;
field.in_handler_priv = NULL;
jtag_add_dr_scan(1, &field, TAP_RTI);
jtag_add_dr_scan(1, &field, TAP_IDLE);
jtag_execute_queue();
status = str9xpec_isc_status(tap);
@ -390,7 +390,7 @@ int str9xpec_blank_check(struct flash_bank_s *bank, int first, int last)
}
/* execute ISC_BLANK_CHECK command */
str9xpec_set_instr(tap, ISC_BLANK_CHECK, TAP_PI);
str9xpec_set_instr(tap, ISC_BLANK_CHECK, TAP_IRPAUSE);
field.tap = tap;
field.num_bits = 64;
@ -402,7 +402,7 @@ int str9xpec_blank_check(struct flash_bank_s *bank, int first, int last)
field.in_handler = NULL;
field.in_handler_priv = NULL;
jtag_add_dr_scan(1, &field, TAP_RTI);
jtag_add_dr_scan(1, &field, TAP_IDLE);
jtag_add_sleep(40000);
/* read blank check result */
@ -416,7 +416,7 @@ int str9xpec_blank_check(struct flash_bank_s *bank, int first, int last)
field.in_handler = NULL;
field.in_handler_priv = NULL;
jtag_add_dr_scan(1, &field, TAP_PI);
jtag_add_dr_scan(1, &field, TAP_IRPAUSE);
jtag_execute_queue();
status = str9xpec_isc_status(tap);
@ -506,7 +506,7 @@ int str9xpec_erase_area(struct flash_bank_s *bank, int first, int last)
LOG_DEBUG("ISC_ERASE");
/* execute ISC_ERASE command */
str9xpec_set_instr(tap, ISC_ERASE, TAP_PI);
str9xpec_set_instr(tap, ISC_ERASE, TAP_IRPAUSE);
field.tap = tap;
field.num_bits = 64;
@ -518,7 +518,7 @@ int str9xpec_erase_area(struct flash_bank_s *bank, int first, int last)
field.in_handler = NULL;
field.in_handler_priv = NULL;
jtag_add_dr_scan(1, &field, TAP_RTI);
jtag_add_dr_scan(1, &field, TAP_IDLE);
jtag_execute_queue();
jtag_add_sleep(10);
@ -569,9 +569,9 @@ int str9xpec_lock_device(struct flash_bank_s *bank)
str9xpec_set_address(bank, 0x80);
/* execute ISC_PROGRAM command */
str9xpec_set_instr(tap, ISC_PROGRAM_SECURITY, TAP_RTI);
str9xpec_set_instr(tap, ISC_PROGRAM_SECURITY, TAP_IDLE);
str9xpec_set_instr(tap, ISC_NOOP, TAP_PI);
str9xpec_set_instr(tap, ISC_NOOP, TAP_IRPAUSE);
do {
field.tap = tap;
@ -658,7 +658,7 @@ int str9xpec_set_address(struct flash_bank_s *bank, u8 sector)
tap = str9xpec_info->tap;
/* set flash controller address */
str9xpec_set_instr(tap, ISC_ADDRESS_SHIFT, TAP_PI);
str9xpec_set_instr(tap, ISC_ADDRESS_SHIFT, TAP_IRPAUSE);
field.tap = tap;
field.num_bits = 8;
@ -747,7 +747,7 @@ int str9xpec_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
while (dwords_remaining > 0)
{
str9xpec_set_instr(tap, ISC_PROGRAM, TAP_PI);
str9xpec_set_instr(tap, ISC_PROGRAM, TAP_IRPAUSE);
field.tap = tap;
field.num_bits = 64;
@ -759,12 +759,12 @@ int str9xpec_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
field.in_handler = NULL;
field.in_handler_priv = NULL;
jtag_add_dr_scan(1, &field, TAP_RTI);
jtag_add_dr_scan(1, &field, TAP_IDLE);
/* small delay before polling */
jtag_add_sleep(50);
str9xpec_set_instr(tap, ISC_NOOP, TAP_PI);
str9xpec_set_instr(tap, ISC_NOOP, TAP_IRPAUSE);
do {
field.tap = tap;
@ -807,7 +807,7 @@ int str9xpec_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
bytes_written++;
}
str9xpec_set_instr(tap, ISC_PROGRAM, TAP_PI);
str9xpec_set_instr(tap, ISC_PROGRAM, TAP_IRPAUSE);
field.tap = tap;
field.num_bits = 64;
@ -819,12 +819,12 @@ int str9xpec_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
field.in_handler = NULL;
field.in_handler_priv = NULL;
jtag_add_dr_scan(1, &field, TAP_RTI);
jtag_add_dr_scan(1, &field, TAP_IDLE);
/* small delay before polling */
jtag_add_sleep(50);
str9xpec_set_instr(tap, ISC_NOOP, TAP_PI);
str9xpec_set_instr(tap, ISC_NOOP, TAP_IRPAUSE);
do {
field.tap = tap;
@ -889,7 +889,7 @@ int str9xpec_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd
buffer = calloc(CEIL(32, 8), 1);
str9xpec_set_instr(tap, ISC_IDCODE, TAP_PI);
str9xpec_set_instr(tap, ISC_IDCODE, TAP_IRPAUSE);
field.tap = tap;
field.num_bits = 32;
@ -901,7 +901,7 @@ int str9xpec_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd
field.in_handler = NULL;
field.in_handler_priv = NULL;
jtag_add_dr_scan(1, &field, TAP_RTI);
jtag_add_dr_scan(1, &field, TAP_IDLE);
jtag_execute_queue();
idcode = buf_get_u32(buffer, 0, 32);
@ -1014,7 +1014,7 @@ int str9xpec_write_options(struct flash_bank_s *bank)
str9xpec_set_address(bank, 0x50);
/* execute ISC_PROGRAM command */
str9xpec_set_instr(tap, ISC_PROGRAM, TAP_PI);
str9xpec_set_instr(tap, ISC_PROGRAM, TAP_IRPAUSE);
field.tap = tap;
field.num_bits = 64;
@ -1026,12 +1026,12 @@ int str9xpec_write_options(struct flash_bank_s *bank)
field.in_handler = NULL;
field.in_handler_priv = NULL;
jtag_add_dr_scan(1, &field, TAP_RTI);
jtag_add_dr_scan(1, &field, TAP_IDLE);
/* small delay before polling */
jtag_add_sleep(50);
str9xpec_set_instr(tap, ISC_NOOP, TAP_PI);
str9xpec_set_instr(tap, ISC_NOOP, TAP_IRPAUSE);
do {
field.tap = tap;
@ -1303,7 +1303,7 @@ int str9xpec_handle_flash_enable_turbo_command(struct command_context_s *cmd_ctx
}
/* enable turbo mode - TURBO-PROG-ENABLE */
str9xpec_set_instr(tap2, 0xD, TAP_RTI);
str9xpec_set_instr(tap2, 0xD, TAP_IDLE);
if ((retval = jtag_execute_queue()) != ERROR_OK)
return retval;
@ -1339,7 +1339,7 @@ int str9xpec_handle_flash_disable_turbo_command(struct command_context_s *cmd_ct
return ERROR_FAIL;
/* exit turbo mode via TLR */
str9xpec_set_instr(tap, ISC_NOOP, TAP_TLR);
str9xpec_set_instr(tap, ISC_NOOP, TAP_RESET);
jtag_execute_queue();
/* restore previous scan chain */

20
src/jtag/amt_jtagaccel.c
View File

@ -215,9 +215,9 @@ void amt_jtagaccel_runtest(int num_cycles)
enum tap_state saved_end_state = end_state;
/* only do a state_move when we're not already in RTI */
if (cur_state != TAP_RTI)
if (cur_state != TAP_IDLE)
{
amt_jtagaccel_end_state(TAP_RTI);
amt_jtagaccel_end_state(TAP_IDLE);
amt_jtagaccel_state_move();
}
@ -251,9 +251,9 @@ void amt_jtagaccel_scan(int ir_scan, enum scan_type type, u8 *buffer, int scan_s
u8 tms_scan[2];
if (ir_scan)
amt_jtagaccel_end_state(TAP_SI);
amt_jtagaccel_end_state(TAP_IRSHIFT);
else
amt_jtagaccel_end_state(TAP_SD);
amt_jtagaccel_end_state(TAP_DRSHIFT);
amt_jtagaccel_state_move();
amt_jtagaccel_end_state(saved_end_state);
@ -351,7 +351,7 @@ int amt_jtagaccel_execute_queue(void)
#endif
if (cmd->cmd.reset->trst == 1)
{
cur_state = TAP_TLR;
cur_state = TAP_RESET;
}
amt_jtagaccel_reset(cmd->cmd.reset->trst, cmd->cmd.reset->srst);
break;
@ -409,16 +409,16 @@ int amt_jtagaccel_get_giveio_access(void)
version.dwOSVersionInfoSize = sizeof version;
if (!GetVersionEx( &version )) {
errno = EINVAL;
return -1;
errno = EINVAL;
return -1;
}
if (version.dwPlatformId != VER_PLATFORM_WIN32_NT)
return 0;
return 0;
h = CreateFile( "\\\\.\\giveio", GENERIC_READ, 0, NULL, OPEN_EXISTING, FILE_ATTRIBUTE_NORMAL, NULL );
if (h == INVALID_HANDLE_VALUE) {
errno = ENODEV;
return -1;
errno = ENODEV;
return -1;
}
CloseHandle( h );

24
src/jtag/bitbang.c
View File

@ -46,11 +46,11 @@ bitbang_interface_t *bitbang_interface;
*
* If someone can submit a patch with an explanation it will be greatly
* appreciated, but as far as I can tell (ØH) DCLK is generated upon
* clk=0 in TAP_RTI. Good luck deducing that from the ARM documentation!
* The ARM documentation uses the term "DCLK is asserted while in the TAP_RTI
* clk=0 in TAP_IDLE. Good luck deducing that from the ARM documentation!
* The ARM documentation uses the term "DCLK is asserted while in the TAP_IDLE
* state". With hardware there is no such thing as *while* in a state. There
* are only edges. So clk => 0 is in fact a very subtle state transition that
* happens *while* in the TAP_RTI state. "#&¤"#¤&"#&"#&
* happens *while* in the TAP_IDLE state. "#&¤"#¤&"#&"#&
*
* For "reset halt" the last thing that happens before srst is asserted
* is that the breakpoint is set up. If DCLK is not wiggled one last
@ -134,9 +134,9 @@ void bitbang_runtest(int num_cycles)
enum tap_state saved_end_state = end_state;
/* only do a state_move when we're not already in RTI */
if (cur_state != TAP_RTI)
if (cur_state != TAP_IDLE)
{
bitbang_end_state(TAP_RTI);
bitbang_end_state(TAP_IDLE);
bitbang_state_move();
}
@ -159,12 +159,12 @@ void bitbang_scan(int ir_scan, enum scan_type type, u8 *buffer, int scan_size)
enum tap_state saved_end_state = end_state;
int bit_cnt;
if (!((!ir_scan && (cur_state == TAP_SD)) || (ir_scan && (cur_state == TAP_SI))))
if (!((!ir_scan && (cur_state == TAP_DRSHIFT)) || (ir_scan && (cur_state == TAP_IRSHIFT))))
{
if (ir_scan)
bitbang_end_state(TAP_SI);
bitbang_end_state(TAP_IRSHIFT);
else
bitbang_end_state(TAP_SD);
bitbang_end_state(TAP_DRSHIFT);
bitbang_state_move();
bitbang_end_state(saved_end_state);
@ -202,7 +202,7 @@ void bitbang_scan(int ir_scan, enum scan_type type, u8 *buffer, int scan_size)
}
}
/* TAP_SD & TAP_SI are illegal end states, so we always transition to the pause
/* TAP_DRSHIFT & TAP_IRSHIFT are illegal end states, so we always transition to the pause
* state which is a legal stable state from which statemove will work.
*
* Exit1 -> Pause
@ -212,9 +212,9 @@ void bitbang_scan(int ir_scan, enum scan_type type, u8 *buffer, int scan_size)
bitbang_interface->write(CLOCK_IDLE(), 0, 0);
if (ir_scan)
cur_state = TAP_PI;
cur_state = TAP_IRPAUSE;
else
cur_state = TAP_PD;
cur_state = TAP_DRPAUSE;
if (cur_state != end_state)
bitbang_state_move();
@ -259,7 +259,7 @@ int bitbang_execute_queue(void)
#endif
if ((cmd->cmd.reset->trst == 1) || (cmd->cmd.reset->srst && (jtag_reset_config & RESET_SRST_PULLS_TRST)))
{
cur_state = TAP_TLR;
cur_state = TAP_RESET;
}
bitbang_interface->reset(cmd->cmd.reset->trst, cmd->cmd.reset->srst);
break;

12
src/jtag/bitq.c
View File

@ -195,7 +195,7 @@ void bitq_runtest(int num_cycles)
int i;
/* only do a state_move when we're not already in RTI */
if (cur_state != TAP_RTI) bitq_state_move(TAP_RTI);
if (cur_state != TAP_IDLE) bitq_state_move(TAP_IDLE);
/* execute num_cycles */
for (i = 0; i < num_cycles; i++)
@ -240,8 +240,8 @@ void bitq_scan_field(scan_field_t *field, int pause)
if (pause) {
bitq_io(0,0,0);
if (cur_state==TAP_SI) cur_state=TAP_PI;
else if (cur_state==TAP_SD) cur_state=TAP_PD;
if (cur_state==TAP_IRSHIFT) cur_state=TAP_IRPAUSE;
else if (cur_state==TAP_DRSHIFT) cur_state=TAP_DRPAUSE;
}
}
@ -250,8 +250,8 @@ void bitq_scan(scan_command_t *cmd)
{
int i;
if (cmd->ir_scan) bitq_state_move(TAP_SI);
else bitq_state_move(TAP_SD);
if (cmd->ir_scan) bitq_state_move(TAP_IRSHIFT);
else bitq_state_move(TAP_DRSHIFT);
for (i=0; i < cmd->num_fields-1; i++)
bitq_scan_field(&cmd->fields[i], 0);
@ -285,7 +285,7 @@ int bitq_execute_queue(void)
#endif
if ((cmd->cmd.reset->trst == 1) || (cmd->cmd.reset->srst && (jtag_reset_config & RESET_SRST_PULLS_TRST)))
{
cur_state = TAP_TLR;
cur_state = TAP_RESET;
}
bitq_interface->reset(cmd->cmd.reset->trst, cmd->cmd.reset->srst);
if (bitq_interface->in_rdy()) bitq_in_proc();

42
src/jtag/ft2232.c
View File

@ -547,7 +547,7 @@ void ft2232_add_scan(int ir_scan, enum scan_type type, u8 *buffer, int scan_size
int cur_byte = 0;
int last_bit;
if (!((!ir_scan && (cur_state == TAP_SD)) || (ir_scan && (cur_state == TAP_SI))))
if (!((!ir_scan && (cur_state == TAP_DRSHIFT)) || (ir_scan && (cur_state == TAP_IRSHIFT))))
{
/* command "Clock Data to TMS/CS Pin (no Read)" */
BUFFER_ADD = 0x4b;
@ -556,13 +556,13 @@ void ft2232_add_scan(int ir_scan, enum scan_type type, u8 *buffer, int scan_size
/* TMS data bits */
if (ir_scan)
{
BUFFER_ADD = TAP_MOVE(cur_state, TAP_SI);
cur_state = TAP_SI;
BUFFER_ADD = TAP_MOVE(cur_state, TAP_IRSHIFT);
cur_state = TAP_IRSHIFT;
}
else
{
BUFFER_ADD = TAP_MOVE(cur_state, TAP_SD);
cur_state = TAP_SD;
BUFFER_ADD = TAP_MOVE(cur_state, TAP_DRSHIFT);
cur_state = TAP_DRSHIFT;
}
/* LOG_DEBUG("added TMS scan (no read)"); */
}
@ -641,8 +641,8 @@ void ft2232_add_scan(int ir_scan, enum scan_type type, u8 *buffer, int scan_size
BUFFER_ADD = buffer[cur_byte];
}
if ((ir_scan && (end_state == TAP_SI)) ||
(!ir_scan && (end_state == TAP_SD)))
if ((ir_scan && (end_state == TAP_IRSHIFT)) ||
(!ir_scan && (end_state == TAP_DRSHIFT)))
{
if (type == SCAN_IO)
{
@ -705,15 +705,15 @@ int ft2232_large_scan(scan_command_t *cmd, enum scan_type type, u8 *buffer, int
exit(-1);
}
if (cur_state != TAP_SD)
if (cur_state != TAP_DRSHIFT)
{
/* command "Clock Data to TMS/CS Pin (no Read)" */
BUFFER_ADD = 0x4b;
/* scan 7 bit */
BUFFER_ADD = 0x6;
/* TMS data bits */
BUFFER_ADD = TAP_MOVE(cur_state, TAP_SD);
cur_state = TAP_SD;
BUFFER_ADD = TAP_MOVE(cur_state, TAP_DRSHIFT);
cur_state = TAP_DRSHIFT;
}
if ((retval = ft2232_write(ft2232_buffer, ft2232_buffer_size, &bytes_written)) != ERROR_OK)
@ -824,7 +824,7 @@ int ft2232_large_scan(scan_command_t *cmd, enum scan_type type, u8 *buffer, int
thisrun_read += 2;
}
if (end_state == TAP_SD)
if (end_state == TAP_DRSHIFT)
{
if (type == SCAN_IO)
{
@ -897,7 +897,7 @@ int ft2232_predict_scan_out(int scan_size, enum scan_type type)
int predicted_size = 3;
int num_bytes = (scan_size - 1) / 8;
if (cur_state != TAP_SD)
if (cur_state != TAP_DRSHIFT)
predicted_size += 3;
if (type == SCAN_IN) /* only from device to host */
@ -1052,7 +1052,7 @@ void axm0432_jtag_reset(int trst, int srst)
{
if (trst == 1)
{
cur_state = TAP_TLR;
cur_state = TAP_RESET;
high_output &= ~nTRST;
}
else if (trst == 0)
@ -1227,7 +1227,7 @@ int ft2232_execute_queue()
if ((cmd->cmd.reset->trst == 1) || (cmd->cmd.reset->srst && (jtag_reset_config & RESET_SRST_PULLS_TRST)))
{
cur_state = TAP_TLR;
cur_state = TAP_RESET;
}
layout->reset(cmd->cmd.reset->trst, cmd->cmd.reset->srst);
require_send = 1;
@ -1239,12 +1239,12 @@ int ft2232_execute_queue()
case JTAG_RUNTEST:
/* only send the maximum buffer size that FT2232C can handle */
predicted_size = 0;
if (cur_state != TAP_RTI)
if (cur_state != TAP_IDLE)
predicted_size += 3;
predicted_size += 3 * CEIL(cmd->cmd.runtest->num_cycles, 7);
if ((cmd->cmd.runtest->end_state != -1) && (cmd->cmd.runtest->end_state != TAP_RTI))
if ((cmd->cmd.runtest->end_state != -1) && (cmd->cmd.runtest->end_state != TAP_IDLE))
predicted_size += 3;
if ((cmd->cmd.runtest->end_state == -1) && (end_state != TAP_RTI))
if ((cmd->cmd.runtest->end_state == -1) && (end_state != TAP_IDLE))
predicted_size += 3;
if (ft2232_buffer_size + predicted_size + 1 > FT2232_BUFFER_SIZE)
{
@ -1253,15 +1253,15 @@ int ft2232_execute_queue()
require_send = 0;
first_unsent = cmd;
}
if (cur_state != TAP_RTI)
if (cur_state != TAP_IDLE)
{
/* command "Clock Data to TMS/CS Pin (no Read)" */
BUFFER_ADD = 0x4b;
/* scan 7 bit */
BUFFER_ADD = 0x6;
/* TMS data bits */
BUFFER_ADD = TAP_MOVE(cur_state, TAP_RTI);
cur_state = TAP_RTI;
BUFFER_ADD = TAP_MOVE(cur_state, TAP_IDLE);
cur_state = TAP_IDLE;
require_send = 1;
}
i = cmd->cmd.runtest->num_cycles;
@ -1273,7 +1273,7 @@ int ft2232_execute_queue()
BUFFER_ADD = (i > 7) ? 6 : (i - 1);
/* TMS data bits */
BUFFER_ADD = 0x0;
cur_state = TAP_RTI;
cur_state = TAP_IDLE;
i -= (i > 7) ? 7 : i;
/* LOG_DEBUG("added TMS scan (no read)"); */
}

34
src/jtag/gw16012.c
View File

@ -258,9 +258,9 @@ void gw16012_runtest(int num_cycles)
int i;
/* only do a state_move when we're not already in RTI */
if (cur_state != TAP_RTI)
if (cur_state != TAP_IDLE)
{
gw16012_end_state(TAP_RTI);
gw16012_end_state(TAP_IDLE);
gw16012_state_move();
}
@ -283,12 +283,12 @@ void gw16012_scan(int ir_scan, enum scan_type type, u8 *buffer, int scan_size)
u8 scan_out, scan_in;
/* only if we're not already in the correct Shift state */
if (!((!ir_scan && (cur_state == TAP_SD)) || (ir_scan && (cur_state == TAP_SI))))
if (!((!ir_scan && (cur_state == TAP_DRSHIFT)) || (ir_scan && (cur_state == TAP_IRSHIFT))))
{
if (ir_scan)
gw16012_end_state(TAP_SI);
gw16012_end_state(TAP_IRSHIFT);
else
gw16012_end_state(TAP_SD);
gw16012_end_state(TAP_DRSHIFT);
gw16012_state_move();
gw16012_end_state(saved_end_state);
@ -312,8 +312,8 @@ void gw16012_scan(int ir_scan, enum scan_type type, u8 *buffer, int scan_size)
if (bits_left == 0) /* last bit */
{
if ((ir_scan && (end_state == TAP_SI))
|| (!ir_scan && (end_state == TAP_SD)))
if ((ir_scan && (end_state == TAP_IRSHIFT))
|| (!ir_scan && (end_state == TAP_DRSHIFT)))
{
tms = 0;
}
@ -334,14 +334,14 @@ void gw16012_scan(int ir_scan, enum scan_type type, u8 *buffer, int scan_size)
bit_count++;
}
if (!((ir_scan && (end_state == TAP_SI)) ||
(!ir_scan && (end_state == TAP_SD))))
if (!((ir_scan && (end_state == TAP_IRSHIFT)) ||
(!ir_scan && (end_state == TAP_DRSHIFT))))
{
gw16012_data(0x0);
if (ir_scan)
cur_state = TAP_PI;
cur_state = TAP_IRPAUSE;
else
cur_state = TAP_PD;
cur_state = TAP_DRPAUSE;
if (cur_state != end_state)
gw16012_state_move();
@ -378,7 +378,7 @@ int gw16012_execute_queue(void)
#endif
if (cmd->cmd.reset->trst == 1)
{
cur_state = TAP_TLR;
cur_state = TAP_RESET;
}
gw16012_reset(cmd->cmd.reset->trst, cmd->cmd.reset->srst);
break;
@ -443,16 +443,16 @@ int gw16012_get_giveio_access()
version.dwOSVersionInfoSize = sizeof version;
if (!GetVersionEx( &version )) {
errno = EINVAL;
return -1;
errno = EINVAL;
return -1;
}
if (version.dwPlatformId != VER_PLATFORM_WIN32_NT)
return 0;
return 0;
h = CreateFile( "\\\\.\\giveio", GENERIC_READ, 0, NULL, OPEN_EXISTING, FILE_ATTRIBUTE_NORMAL, NULL );
if (h == INVALID_HANDLE_VALUE) {
errno = ENODEV;
return -1;
errno = ENODEV;
return -1;
}
CloseHandle( h );

10
src/jtag/jlink.c
View File

@ -214,7 +214,7 @@ int jlink_execute_queue(void)
if (cmd->cmd.reset->trst == 1)
{
cur_state = TAP_TLR;
cur_state = TAP_RESET;
}
jlink_reset(cmd->cmd.reset->trst, cmd->cmd.reset->srst);
break;
@ -393,9 +393,9 @@ void jlink_runtest(int num_cycles)
enum tap_state saved_end_state = end_state;
/* only do a state_move when we're not already in RTI */
if (cur_state != TAP_RTI)
if (cur_state != TAP_IDLE)
{
jlink_end_state(TAP_RTI);
jlink_end_state(TAP_IDLE);
jlink_state_move();
}
@ -422,7 +422,7 @@ void jlink_scan(int ir_scan, enum scan_type type, u8 *buffer, int scan_size, sca
saved_end_state = end_state;
/* Move to appropriate scan state */
jlink_end_state(ir_scan ? TAP_SI : TAP_SD);
jlink_end_state(ir_scan ? TAP_IRSHIFT : TAP_DRSHIFT);
jlink_state_move();
jlink_end_state(saved_end_state);
@ -433,7 +433,7 @@ void jlink_scan(int ir_scan, enum scan_type type, u8 *buffer, int scan_size, sca
/* We are in Exit1, go to Pause */
jlink_tap_append_step(0, 0);
cur_state = ir_scan ? TAP_PI : TAP_PD;
cur_state = ir_scan ? TAP_IRPAUSE : TAP_DRPAUSE;
if (cur_state != end_state)
{

62
src/jtag/jtag.c
View File

@ -87,22 +87,22 @@ int tap_move_map[16] = {
tap_transition_t tap_transitions[16] =
{
{TAP_TLR, TAP_RTI}, /* TLR */
{TAP_SIS, TAP_CD}, /* SDS */
{TAP_E1D, TAP_SD}, /* CD */
{TAP_E1D, TAP_SD}, /* SD */
{TAP_UD, TAP_PD}, /* E1D */
{TAP_E2D, TAP_PD}, /* PD */
{TAP_UD, TAP_SD}, /* E2D */
{TAP_SDS, TAP_RTI}, /* UD */
{TAP_SDS, TAP_RTI}, /* RTI */
{TAP_TLR, TAP_CI}, /* SIS */
{TAP_E1I, TAP_SI}, /* CI */
{TAP_E1I, TAP_SI}, /* SI */
{TAP_UI, TAP_PI}, /* E1I */
{TAP_E2I, TAP_PI}, /* PI */
{TAP_UI, TAP_SI}, /* E2I */
{TAP_SDS, TAP_RTI} /* UI */
{TAP_RESET, TAP_IDLE}, /* TLR */
{TAP_IRSELECT, TAP_DRCAPTURE}, /* SDS */
{TAP_DREXIT1, TAP_DRSHIFT}, /* CD */
{TAP_DREXIT1, TAP_DRSHIFT}, /* SD */
{TAP_DRUPDATE, TAP_DRPAUSE}, /* E1D */
{TAP_DREXIT2, TAP_DRPAUSE}, /* PD */
{TAP_DRUPDATE, TAP_DRSHIFT}, /* E2D */
{TAP_DRSELECT, TAP_IDLE}, /* UD */
{TAP_DRSELECT, TAP_IDLE}, /* RTI */
{TAP_RESET, TAP_IRCAPTURE}, /* SIS */
{TAP_IREXIT1, TAP_IRSHIFT}, /* CI */
{TAP_IREXIT1, TAP_IRSHIFT}, /* SI */
{TAP_IRUPDATE, TAP_IRPAUSE}, /* E1I */
{TAP_IREXIT2, TAP_IRPAUSE}, /* PI */
{TAP_IRUPDATE, TAP_IRSHIFT}, /* E2I */
{TAP_DRSELECT, TAP_IDLE} /* UI */
};
char* jtag_event_strings[] =
@ -115,8 +115,8 @@ char* jtag_event_strings[] =
* inside the drivers, but we don't want to break
* linking the drivers!!!!
*/
enum tap_state end_state = TAP_TLR;
enum tap_state cur_state = TAP_TLR;
enum tap_state end_state = TAP_RESET;
enum tap_state cur_state = TAP_RESET;
int jtag_trst = 0;
int jtag_srst = 0;
@ -125,8 +125,8 @@ jtag_command_t **last_comand_pointer = &jtag_command_queue;
static jtag_tap_t *jtag_all_taps = NULL;
enum reset_types jtag_reset_config = RESET_NONE;
enum tap_state cmd_queue_end_state = TAP_TLR;
enum tap_state cmd_queue_cur_state = TAP_TLR;
enum tap_state cmd_queue_end_state = TAP_RESET;
enum tap_state cmd_queue_cur_state = TAP_RESET;
int jtag_verify_capture_ir = 1;
@ -543,7 +543,7 @@ static void jtag_prelude1(void)
return;
}
if (cmd_queue_end_state == TAP_TLR)
if (cmd_queue_end_state == TAP_RESET)
jtag_call_event_callbacks(JTAG_TRST_ASSERTED);
}
@ -959,7 +959,7 @@ int MINIDRIVER(interface_jtag_add_plain_dr_scan)(int num_fields, scan_field_t *f
void jtag_add_tlr(void)
{
jtag_prelude(TAP_TLR);
jtag_prelude(TAP_RESET);
int retval;
retval=interface_jtag_add_tlr();
@ -969,7 +969,7 @@ void jtag_add_tlr(void)
int MINIDRIVER(interface_jtag_add_tlr)()
{
enum tap_state state = TAP_TLR;
enum tap_state state = TAP_RESET;
jtag_command_t **last_cmd = jtag_get_last_command_p();
/* allocate memory for a new list member */
@ -1000,9 +1000,9 @@ void jtag_add_pathmove(int num_states, enum tap_state *path)
for (i=0; i<num_states; i++)
{
if (path[i] == TAP_TLR)
if (path[i] == TAP_RESET)
{
LOG_ERROR("BUG: TAP_TLR is not a valid state for pathmove sequences");
LOG_ERROR("BUG: TAP_RESET is not a valid state for pathmove sequences");
exit(-1);
}
if ((tap_transitions[cur_state].low != path[i])&&
@ -1154,7 +1154,7 @@ void jtag_add_reset(int req_tlr_or_trst, int req_srst)
if (trst_with_tlr)
{
LOG_DEBUG("JTAG reset with TLR instead of TRST");
jtag_add_end_state(TAP_TLR);
jtag_add_end_state(TAP_RESET);
jtag_add_tlr();
jtag_call_event_callbacks(JTAG_TRST_ASSERTED);
return;
@ -1166,7 +1166,7 @@ void jtag_add_reset(int req_tlr_or_trst, int req_srst)
* and inform possible listeners about this
*/
LOG_DEBUG("TRST line asserted");
cmd_queue_cur_state = TAP_TLR;
cmd_queue_cur_state = TAP_RESET;
jtag_call_event_callbacks(JTAG_TRST_ASSERTED);
}
else
@ -1196,9 +1196,9 @@ int MINIDRIVER(interface_jtag_add_reset)(int req_trst, int req_srst)
void jtag_add_end_state(enum tap_state state)
{
cmd_queue_end_state = state;
if ((cmd_queue_end_state == TAP_SD)||(cmd_queue_end_state == TAP_SI))
if ((cmd_queue_end_state == TAP_DRSHIFT)||(cmd_queue_end_state == TAP_IRSHIFT))
{
LOG_ERROR("BUG: TAP_SD/SI can't be end state. Calling code should use a larger scan field");
LOG_ERROR("BUG: TAP_DRSHIFT/SI can't be end state. Calling code should use a larger scan field");
}
}
@ -1491,7 +1491,7 @@ int jtag_examine_chain(void)
buf_set_u32(idcode_buffer, i * 32, 32, 0x000000FF);
}
jtag_add_plain_dr_scan(1, &field, TAP_TLR);
jtag_add_plain_dr_scan(1, &field, TAP_RESET);
jtag_execute_queue();
for (i = 0; i < JTAG_MAX_CHAIN_SIZE * 4; i++)
@ -1662,7 +1662,7 @@ int jtag_validate_chain(void)
field.in_handler = NULL;
field.in_handler_priv = NULL;
jtag_add_plain_ir_scan(1, &field, TAP_TLR);
jtag_add_plain_ir_scan(1, &field, TAP_RESET);
jtag_execute_queue();
tap = NULL;

33
src/jtag/jtag.h
View File

@ -33,20 +33,15 @@
#define _DEBUG_JTAG_IO_
#endif
/* Tap States
* TLR - Test-Logic-Reset, RTI - Run-Test/Idle,
* SDS - Select-DR-Scan, CD - Capture-DR, SD - Shift-DR, E1D - Exit1-DR,
* PD - Pause-DR, E2D - Exit2-DR, UD - Update-DR,
* SIS - Select-IR-Scan, CI - Capture-IR, SI - Shift-IR, E1I - Exit1-IR,
* PI - Pause-IR, E2I - Exit2-IR, UI - Update-IR
/* 16 Tap States, from page 21 of ASSET InterTech, Inc.'s svf.pdf
*/
enum tap_state
{
TAP_TLR = 0x0, TAP_RTI = 0x8,
TAP_SDS = 0x1, TAP_CD = 0x2, TAP_SD = 0x3, TAP_E1D = 0x4,
TAP_PD = 0x5, TAP_E2D = 0x6, TAP_UD = 0x7,
TAP_SIS = 0x9, TAP_CI = 0xa, TAP_SI = 0xb, TAP_E1I = 0xc,
TAP_PI = 0xd, TAP_E2I = 0xe, TAP_UI = 0xf
TAP_RESET = 0x0, TAP_IDLE = 0x8,
TAP_DRSELECT = 0x1, TAP_DRCAPTURE = 0x2, TAP_DRSHIFT = 0x3, TAP_DREXIT1 = 0x4,
TAP_DRPAUSE = 0x5, TAP_DREXIT2 = 0x6, TAP_DRUPDATE = 0x7,
TAP_IRSELECT = 0x9, TAP_IRCAPTURE = 0xa, TAP_IRSHIFT = 0xb, TAP_IREXIT1 = 0xc,
TAP_IRPAUSE = 0xd, TAP_IREXIT2 = 0xe, TAP_IRUPDATE = 0xf
};
typedef struct tap_transition_s
@ -325,7 +320,7 @@ extern int jtag_register_commands(struct command_context_s *cmd_ctx);
/* JTAG interface, can be implemented with a software or hardware fifo
*
* TAP_SD and TAP_SI are illegal end states. TAP_SD/SI as end states
* TAP_DRSHIFT and TAP_IRSHIFT are illegal end states. TAP_DRSHIFT/SI as end states
* can be emulated by using a larger scan.
*
* Code that is relatively insensitive to the path(as long
@ -343,7 +338,7 @@ extern void jtag_add_plain_ir_scan(int num_fields, scan_field_t *fields, enum ta
extern int interface_jtag_add_plain_ir_scan(int num_fields, scan_field_t *fields, enum tap_state endstate);
extern void jtag_add_plain_dr_scan(int num_fields, scan_field_t *fields, enum tap_state endstate);
extern int interface_jtag_add_plain_dr_scan(int num_fields, scan_field_t *fields, enum tap_state endstate);
/* run a TAP_TLR reset. End state is TAP_TLR, regardless
/* run a TAP_RESET reset. End state is TAP_RESET, regardless
* of start state.
*/
extern void jtag_add_tlr(void);
@ -364,7 +359,7 @@ extern int interface_jtag_add_tlr(void);
* all drivers can support this, but it is required for e.g.
* XScale and Xilinx support
*
* Note! TAP_TLR must not be used in the path!
* Note! TAP_RESET must not be used in the path!
*
* Note that the first on the list must be reachable
* via a single transition from the current state.
@ -380,12 +375,12 @@ extern int interface_jtag_add_tlr(void);
*/
extern void jtag_add_pathmove(int num_states, enum tap_state *path);
extern int interface_jtag_add_pathmove(int num_states, enum tap_state *path);
/* go to TAP_RTI, if we're not already there and cycle
* precisely num_cycles in the TAP_RTI after which move
* to the end state, if it is != TAP_RTI
/* go to TAP_IDLE, if we're not already there and cycle
* precisely num_cycles in the TAP_IDLE after which move
* to the end state, if it is != TAP_IDLE
*
* nb! num_cycles can be 0, in which case the fn will navigate
* to endstate via TAP_RTI
* to endstate via TAP_IDLE
*/
extern void jtag_add_runtest(int num_cycles, enum tap_state endstate);
extern int interface_jtag_add_runtest(int num_cycles, enum tap_state endstate);
@ -488,7 +483,7 @@ extern int jtag_verify_capture_ir;
#define MINIDRIVER(a) a
/* jtag_add_dr_out() is a faster version of jtag_add_dr_scan()
*
* Current or end_state can not be TAP_TLR. end_state can be -1
* Current or end_state can not be TAP_RESET. end_state can be -1
*
* num_bits[i] is the number of bits to clock out from value[i] LSB first.
*

14
src/jtag/usbprog.c
View File

@ -151,7 +151,7 @@ int usbprog_execute_queue(void)
#endif
if (cmd->cmd.reset->trst == 1)
{
cur_state = TAP_TLR;
cur_state = TAP_RESET;
}
usbprog_reset(cmd->cmd.reset->trst, cmd->cmd.reset->srst);
break;
@ -299,9 +299,9 @@ void usbprog_runtest(int num_cycles)
int i;
/* only do a state_move when we're not already in RTI */
if (cur_state != TAP_RTI)
if (cur_state != TAP_IDLE)
{
usbprog_end_state(TAP_RTI);
usbprog_end_state(TAP_IDLE);
usbprog_state_move();
}
@ -336,9 +336,9 @@ void usbprog_scan(int ir_scan, enum scan_type type, u8 *buffer, int scan_size)
enum tap_state saved_end_state = end_state;
if (ir_scan)
usbprog_end_state(TAP_SI);
usbprog_end_state(TAP_IRSHIFT);
else
usbprog_end_state(TAP_SD);
usbprog_end_state(TAP_DRSHIFT);
/* usbprog_jtag_tms_send(usbprog_jtag_handle); */
@ -361,9 +361,9 @@ void usbprog_scan(int ir_scan, enum scan_type type, u8 *buffer, int scan_size)
}
if (ir_scan)
cur_state = TAP_PI;
cur_state = TAP_IRPAUSE;
else
cur_state = TAP_PD;
cur_state = TAP_DRPAUSE;
if (cur_state != end_state)
usbprog_state_move();

38
src/jtag/zy1000.c
View File

@ -158,7 +158,7 @@ void zy1000_reset(int trst, int srst)
else
{
/* Danger!!! if clk!=0 when in
* idle in TAP_RTI, reset halt on str912 will fail.
* idle in TAP_IDLE, reset halt on str912 will fail.
*/
ZY1000_POKE(ZY1000_JTAG_BASE+0x10, 0x00000001);
}
@ -177,7 +177,7 @@ void zy1000_reset(int trst, int srst)
{
waitIdle();
/* we're now in the TLR state until trst is deasserted */
ZY1000_POKE(ZY1000_JTAG_BASE+0x20, TAP_TLR);
ZY1000_POKE(ZY1000_JTAG_BASE+0x20, TAP_RESET);
} else
{
/* We'll get RCLK failure when we assert TRST, so clear any false positives here */
@ -303,7 +303,7 @@ int loadFile(const char *fileName, void **data, int *len)
if (fread(*data, 1, *len, pFile)!=*len)
{
fclose(pFile);
free(*data);
free(*data);
LOG_ERROR("Can't open %s\n", fileName);
return ERROR_JTAG_DEVICE_ERROR;
}
@ -429,7 +429,7 @@ static __inline void scanFields(int num_fields, scan_field_t *fields, enum tap_s
enum tap_state pause_state;
int l;
k=num_bits-j;
pause_state=(shiftState==TAP_SD)?TAP_SD:TAP_SI;
pause_state=(shiftState==TAP_DRSHIFT)?TAP_DRSHIFT:TAP_IRSHIFT;
if (k>32)
{
k=32;
@ -437,7 +437,7 @@ static __inline void scanFields(int num_fields, scan_field_t *fields, enum tap_s
} else if (pause&&(i == num_fields-1))
{
/* this was the last to shift out this time */
pause_state=(shiftState==TAP_SD)?TAP_PD:TAP_PI;
pause_state=(shiftState==TAP_DRSHIFT)?TAP_DRPAUSE:TAP_IRPAUSE;
}
// we have (num_bits+7)/8 bytes of bits to toggle out.
@ -520,7 +520,7 @@ int interface_jtag_add_ir_scan(int num_fields, scan_field_t *fields, enum tap_st
fields[j].in_check_mask = tap->expected_mask;
}
scanFields(1, fields+j, TAP_SI, pause);
scanFields(1, fields+j, TAP_IRSHIFT, pause);
/* update device information */
buf_cpy(fields[j].out_value, tap->cur_instr, scan_size);
@ -538,7 +538,7 @@ int interface_jtag_add_ir_scan(int num_fields, scan_field_t *fields, enum tap_st
memset(&tmp, 0, sizeof(tmp));
tmp.out_value = ones;
tmp.num_bits = scan_size;
scanFields(1, &tmp, TAP_SI, pause);
scanFields(1, &tmp, TAP_IRSHIFT, pause);
/* update device information */
buf_cpy(tmp.out_value, tap->cur_instr, scan_size);
tap->bypass = 1;
@ -555,7 +555,7 @@ int interface_jtag_add_ir_scan(int num_fields, scan_field_t *fields, enum tap_st
int interface_jtag_add_plain_ir_scan(int num_fields, scan_field_t *fields, enum tap_state state)
{
scanFields(num_fields, fields, TAP_SI, 1);
scanFields(num_fields, fields, TAP_IRSHIFT, 1);
gotoEndState();
return ERROR_OK;
@ -580,7 +580,7 @@ int interface_jtag_add_dr_scan(int num_fields, scan_field_t *fields, enum tap_st
{
found = 1;
scanFields(1, fields+j, TAP_SD, pause);
scanFields(1, fields+j, TAP_DRSHIFT, pause);
}
}
if (!found)
@ -596,7 +596,7 @@ int interface_jtag_add_dr_scan(int num_fields, scan_field_t *fields, enum tap_st
tmp.in_handler = NULL;
tmp.in_handler_priv = NULL;
scanFields(1, &tmp, TAP_SD, pause);
scanFields(1, &tmp, TAP_DRSHIFT, pause);
}
else
{
@ -608,7 +608,7 @@ int interface_jtag_add_dr_scan(int num_fields, scan_field_t *fields, enum tap_st
int interface_jtag_add_plain_dr_scan(int num_fields, scan_field_t *fields, enum tap_state state)
{
scanFields(num_fields, fields, TAP_SD, 1);
scanFields(num_fields, fields, TAP_DRSHIFT, 1);
gotoEndState();
return ERROR_OK;
}
@ -616,7 +616,7 @@ int interface_jtag_add_plain_dr_scan(int num_fields, scan_field_t *fields, enum
int interface_jtag_add_tlr()
{
setCurrentState(TAP_TLR);
setCurrentState(TAP_RESET);
return ERROR_OK;
}
@ -635,7 +635,7 @@ int interface_jtag_add_reset(int req_trst, int req_srst)
int interface_jtag_add_runtest(int num_cycles, enum tap_state state)
{
/* num_cycles can be 0 */
setCurrentState(TAP_RTI);
setCurrentState(TAP_IDLE);
/* execute num_cycles, 32 at the time. */
int i;
@ -647,14 +647,14 @@ int interface_jtag_add_runtest(int num_cycles, enum tap_state state)
{
num=num_cycles-i;
}
shiftValueInner(TAP_RTI, TAP_RTI, num, 0);
shiftValueInner(TAP_IDLE, TAP_IDLE, num, 0);
}
#if !TEST_MANUAL()
/* finish in end_state */
setCurrentState(state);
#else
enum tap_state t=TAP_RTI;
enum tap_state t=TAP_IDLE;
/* test manual drive code on any target */
int tms;
u8 tms_scan = TAP_MOVE(t, state);
@ -734,8 +734,8 @@ void embeddedice_write_dcc(jtag_tap_t *tap, int reg_addr, u8 *buffer, int little
int i;
for (i = 0; i < count; i++)
{
shiftValueInner(TAP_SD, TAP_SD, 32, fast_target_buffer_get_u32(buffer, 1));
shiftValueInner(TAP_SD, end_state, 6, reg_addr|(1<<5));
shiftValueInner(TAP_DRSHIFT, TAP_DRSHIFT, 32, fast_target_buffer_get_u32(buffer, 1));
shiftValueInner(TAP_DRSHIFT, end_state, 6, reg_addr|(1<<5));
buffer+=4;
}
} else
@ -743,8 +743,8 @@ void embeddedice_write_dcc(jtag_tap_t *tap, int reg_addr, u8 *buffer, int little
int i;
for (i = 0; i < count; i++)
{
shiftValueInner(TAP_SD, TAP_SD, 32, fast_target_buffer_get_u32(buffer, 0));
shiftValueInner(TAP_SD, end_state, 6, reg_addr|(1<<5));
shiftValueInner(TAP_DRSHIFT, TAP_DRSHIFT, 32, fast_target_buffer_get_u32(buffer, 0));
shiftValueInner(TAP_DRSHIFT, end_state, 6, reg_addr|(1<<5));
buffer+=4;
}
}

16
src/pld/virtex2.c
View File

@ -63,7 +63,7 @@ int virtex2_set_instr(jtag_tap_t *tap, u32 new_instr)
field.in_handler = NULL;
field.in_handler_priv = NULL;
jtag_add_ir_scan(1, &field, TAP_RTI);
jtag_add_ir_scan(1, &field, TAP_IDLE);
free(field.out_value);
}
@ -95,7 +95,7 @@ int virtex2_send_32(struct pld_device_s *pld_device, int num_words, u32 *words)
virtex2_set_instr(virtex2_info->tap, 0x5); /* CFG_IN */
jtag_add_dr_scan(1, &scan_field, TAP_PD);
jtag_add_dr_scan(1, &scan_field, TAP_DRPAUSE);
free(values);
@ -128,7 +128,7 @@ int virtex2_receive_32(struct pld_device_s *pld_device, int num_words, u32 *word
while (num_words--)
{
scan_field.in_handler_priv = words++;
jtag_add_dr_scan(1, &scan_field, TAP_PD);
jtag_add_dr_scan(1, &scan_field, TAP_DRPAUSE);
}
return ERROR_OK;
@ -176,7 +176,7 @@ int virtex2_load(struct pld_device_s *pld_device, char *filename)
if ((retval = xilinx_read_bit_file(&bit_file, filename)) != ERROR_OK)
return retval;
jtag_add_end_state(TAP_RTI);
jtag_add_end_state(TAP_IDLE);
virtex2_set_instr(virtex2_info->tap, 0xb); /* JPROG_B */
jtag_execute_queue();
jtag_add_sleep(1000);
@ -190,18 +190,18 @@ int virtex2_load(struct pld_device_s *pld_device, char *filename)
field.num_bits = bit_file.length * 8;
field.out_value = bit_file.data;
jtag_add_dr_scan(1, &field, TAP_PD);
jtag_add_dr_scan(1, &field, TAP_DRPAUSE);
jtag_execute_queue();
jtag_add_tlr();
jtag_add_end_state(TAP_RTI);
jtag_add_end_state(TAP_IDLE);
virtex2_set_instr(virtex2_info->tap, 0xc); /* JSTART */
jtag_add_runtest(13, TAP_RTI);
jtag_add_runtest(13, TAP_IDLE);
virtex2_set_instr(virtex2_info->tap, 0x3f); /* BYPASS */
virtex2_set_instr(virtex2_info->tap, 0x3f); /* BYPASS */
virtex2_set_instr(virtex2_info->tap, 0xc); /* JSTART */
jtag_add_runtest(13, TAP_RTI);
jtag_add_runtest(13, TAP_IDLE);
virtex2_set_instr(virtex2_info->tap, 0x3f); /* BYPASS */
jtag_execute_queue();

14
src/target/arm11.c
View File

@ -393,7 +393,7 @@ static void arm11_on_enter_debug_state(arm11_common_t * arm11)
arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1);
arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_PD);
arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
}
else
{
@ -627,7 +627,7 @@ void arm11_leave_debug_state(arm11_common_t * arm11)
arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1);
arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2);
arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_PD);
arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
}
arm11_record_register_history(arm11);
@ -735,7 +735,7 @@ int arm11_halt(struct target_s *target)
return ERROR_OK;
}
arm11_add_IR(arm11, ARM11_HALT, TAP_RTI);
arm11_add_IR(arm11, ARM11_HALT, TAP_IDLE);
if((retval = jtag_execute_queue()) != ERROR_OK)
{
@ -841,7 +841,7 @@ int arm11_resume(struct target_s *target, int current, u32 address, int handle_b
arm11_leave_debug_state(arm11);
arm11_add_IR(arm11, ARM11_RESTART, TAP_RTI);
arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
if((retval = jtag_execute_queue()) != ERROR_OK)
{
@ -956,7 +956,7 @@ int arm11_step(struct target_s *target, int current, u32 address, int handle_bre
arm11_leave_debug_state(arm11);
arm11_add_IR(arm11, ARM11_RESTART, TAP_RTI);
arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
if((retval = jtag_execute_queue()) != ERROR_OK)
{
@ -1571,7 +1571,7 @@ int arm11_examine(struct target_s *target)
arm11_setup_field(arm11, 32, NULL, &arm11->device_id, &idcode_field);
arm11_add_dr_scan_vc(1, &idcode_field, TAP_PD);
arm11_add_dr_scan_vc(1, &idcode_field, TAP_DRPAUSE);
/* check DIDR */
@ -1584,7 +1584,7 @@ int arm11_examine(struct target_s *target)
arm11_setup_field(arm11, 32, NULL, &arm11->didr, chain0_fields + 0);
arm11_setup_field(arm11, 8, NULL, &arm11->implementor, chain0_fields + 1);
arm11_add_dr_scan_vc(asizeof(chain0_fields), chain0_fields, TAP_RTI);
arm11_add_dr_scan_vc(asizeof(chain0_fields), chain0_fields, TAP_IDLE);
if ((retval=jtag_execute_queue())!=ERROR_OK)
return retval;

60
src/target/arm11_dbgtap.c
View File

@ -38,13 +38,13 @@
enum tap_state arm11_move_pi_to_si_via_ci[] =
{
TAP_E2I, TAP_UI, TAP_SDS, TAP_SIS, TAP_CI, TAP_SI
TAP_IREXIT2, TAP_IRUPDATE, TAP_DRSELECT, TAP_IRSELECT, TAP_IRCAPTURE, TAP_IRSHIFT
};
int arm11_add_ir_scan_vc(int num_fields, scan_field_t *fields, enum tap_state state)
{
if (cmd_queue_cur_state == TAP_PI)
if (cmd_queue_cur_state == TAP_IRPAUSE)
jtag_add_pathmove(asizeof(arm11_move_pi_to_si_via_ci), arm11_move_pi_to_si_via_ci);
jtag_add_ir_scan(num_fields, fields, state);
@ -53,12 +53,12 @@ int arm11_add_ir_scan_vc(int num_fields, scan_field_t *fields, enum tap_state st
enum tap_state arm11_move_pd_to_sd_via_cd[] =
{
TAP_E2D, TAP_UD, TAP_SDS, TAP_CD, TAP_SD
TAP_DREXIT2, TAP_DRUPDATE, TAP_DRSELECT, TAP_DRCAPTURE, TAP_DRSHIFT
};
int arm11_add_dr_scan_vc(int num_fields, scan_field_t *fields, enum tap_state state)
{
if (cmd_queue_cur_state == TAP_PD)
if (cmd_queue_cur_state == TAP_DRPAUSE)
jtag_add_pathmove(asizeof(arm11_move_pd_to_sd_via_cd), arm11_move_pd_to_sd_via_cd);
jtag_add_dr_scan(num_fields, fields, state);
@ -104,7 +104,7 @@ void arm11_add_IR(arm11_common_t * arm11, u8 instr, enum tap_state state)
jtag_tap_t *tap;
tap = arm11->jtag_info.tap;
if( tap == NULL ){
/* FIX!!!! error is logged, but not propagated back up the call stack... */
/* FIX!!!! error is logged, but not propagated back up the call stack... */
LOG_ERROR( "tap is null here! This is bad!");
return;
}
@ -120,7 +120,7 @@ void arm11_add_IR(arm11_common_t * arm11, u8 instr, enum tap_state state)
arm11_setup_field(arm11, 5, &instr, NULL, &field);
arm11_add_ir_scan_vc(1, &field, state == -1 ? TAP_PI : state);
arm11_add_ir_scan_vc(1, &field, state == -1 ? TAP_IRPAUSE : state);
}
/** Verify shifted out data from Scan Chain Register (SCREG)
@ -135,8 +135,8 @@ static int arm11_in_handler_SCAN_N(u8 *in_value, void *priv, struct scan_field_s
if (v != 0x10)
{
LOG_ERROR("'arm11 target' JTAG communication error SCREG SCAN OUT 0x%02x (expected 0x10)", v);
return ERROR_FAIL;
LOG_ERROR("'arm11 target' JTAG communication error SCREG SCAN OUT 0x%02x (expected 0x10)", v);
return ERROR_FAIL;
}
JTAG_DEBUG("SCREG SCAN OUT 0x%02x", v);
@ -179,7 +179,7 @@ void arm11_add_debug_SCAN_N(arm11_common_t * arm11, u8 chain, enum tap_state sta
field.in_handler = arm11_in_handler_SCAN_N;
arm11_add_dr_scan_vc(1, &field, state == -1 ? TAP_PD : state);
arm11_add_dr_scan_vc(1, &field, state == -1 ? TAP_DRPAUSE : state);
}
/** Write an instruction into the ITR register
@ -194,7 +194,7 @@ void arm11_add_debug_SCAN_N(arm11_common_t * arm11, u8 chain, enum tap_state sta
* \remarks By default this ends with Run-Test/Idle state
* and causes the instruction to be executed. If
* a subsequent write to DTR is needed before
* executing the instruction then TAP_PD should be
* executing the instruction then TAP_DRPAUSE should be
* passed to \p state.
*
* \remarks This adds to the JTAG command queue but does \em not execute it.
@ -208,7 +208,7 @@ void arm11_add_debug_INST(arm11_common_t * arm11, u32 inst, u8 * flag, enum tap_
arm11_setup_field(arm11, 32, &inst, NULL, itr + 0);
arm11_setup_field(arm11, 1, NULL, flag, itr + 1);
arm11_add_dr_scan_vc(asizeof(itr), itr, state == -1 ? TAP_RTI : state);
arm11_add_dr_scan_vc(asizeof(itr), itr, state == -1 ? TAP_IDLE : state);
}
/** Read the Debug Status and Control Register (DSCR)
@ -231,12 +231,12 @@ u32 arm11_read_DSCR(arm11_common_t * arm11)
arm11_setup_field(arm11, 32, NULL, &dscr, &chain1_field);
arm11_add_dr_scan_vc(1, &chain1_field, TAP_PD);
arm11_add_dr_scan_vc(1, &chain1_field, TAP_DRPAUSE);
jtag_execute_queue();
if (arm11->last_dscr != dscr)
JTAG_DEBUG("DSCR = %08x (OLD %08x)", dscr, arm11->last_dscr);
JTAG_DEBUG("DSCR = %08x (OLD %08x)", dscr, arm11->last_dscr);
arm11->last_dscr = dscr;
@ -262,7 +262,7 @@ void arm11_write_DSCR(arm11_common_t * arm11, u32 dscr)
arm11_setup_field(arm11, 32, &dscr, NULL, &chain1_field);
arm11_add_dr_scan_vc(1, &chain1_field, TAP_PD);
arm11_add_dr_scan_vc(1, &chain1_field, TAP_DRPAUSE);
jtag_execute_queue();
@ -369,13 +369,13 @@ void arm11_run_instr_no_data(arm11_common_t * arm11, u32 * opcode, size_t count)
while (count--)
{
arm11_add_debug_INST(arm11, *opcode++, NULL, TAP_RTI);
arm11_add_debug_INST(arm11, *opcode++, NULL, TAP_IDLE);
while (1)
{
u8 flag;
arm11_add_debug_INST(arm11, 0, &flag, count ? TAP_RTI : TAP_PD);
arm11_add_debug_INST(arm11, 0, &flag, count ? TAP_IDLE : TAP_DRPAUSE);
jtag_execute_queue();
@ -416,7 +416,7 @@ void arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data
{
arm11_add_IR(arm11, ARM11_ITRSEL, -1);
arm11_add_debug_INST(arm11, opcode, NULL, TAP_PD);
arm11_add_debug_INST(arm11, opcode, NULL, TAP_DRPAUSE);
arm11_add_IR(arm11, ARM11_EXTEST, -1);
@ -436,7 +436,7 @@ void arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data
{
Data = *data;
arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_RTI);
arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_IDLE);
jtag_execute_queue();
JTAG_DEBUG("DTR Ready %d nRetry %d", Ready, nRetry);
@ -452,7 +452,7 @@ void arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data
{
Data = 0;
arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_PD);
arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
jtag_execute_queue();
JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data, Ready, nRetry);
@ -462,18 +462,18 @@ void arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data
/** JTAG path for arm11_run_instr_data_to_core_noack
*
* The repeated TAP_RTI's do not cause a repeated execution
* The repeated TAP_IDLE's do not cause a repeated execution
* if passed without leaving the state.
*
* Since this is more than 7 bits (adjustable via adding more
* TAP_RTI's) it produces an artificial delay in the lower
* TAP_IDLE's) it produces an artificial delay in the lower
* layer (FT2232) that is long enough to finish execution on
* the core but still shorter than any manually inducible delays.
*
*/
enum tap_state arm11_MOVE_PD_RTI_PD_with_delay[] =
{
TAP_E2D, TAP_UD, TAP_RTI, TAP_RTI, TAP_RTI, TAP_SDS, TAP_CD, TAP_SD
TAP_DREXIT2, TAP_DRUPDATE, TAP_IDLE, TAP_IDLE, TAP_IDLE, TAP_DRSELECT, TAP_DRCAPTURE, TAP_DRSHIFT
};
@ -497,7 +497,7 @@ void arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, u32 opcode, u32
{
arm11_add_IR(arm11, ARM11_ITRSEL, -1);
arm11_add_debug_INST(arm11, opcode, NULL, TAP_PD);
arm11_add_debug_INST(arm11, opcode, NULL, TAP_DRPAUSE);
arm11_add_IR(arm11, ARM11_EXTEST, -1);
@ -517,13 +517,13 @@ void arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, u32 opcode, u32
if (count)
{
jtag_add_dr_scan(asizeof(chain5_fields), chain5_fields, TAP_PD);
jtag_add_dr_scan(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
jtag_add_pathmove(asizeof(arm11_MOVE_PD_RTI_PD_with_delay),
arm11_MOVE_PD_RTI_PD_with_delay);
}
else
{
jtag_add_dr_scan(asizeof(chain5_fields), chain5_fields, TAP_RTI);
jtag_add_dr_scan(asizeof(chain5_fields), chain5_fields, TAP_IDLE);
}
}
@ -532,7 +532,7 @@ void arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, u32 opcode, u32
chain5_fields[0].out_value = 0;
chain5_fields[1].in_value = ReadyPos++;
arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_PD);
arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
jtag_execute_queue();
@ -586,7 +586,7 @@ void arm11_run_instr_data_from_core(arm11_common_t * arm11, u32 opcode, u32 * da
{
arm11_add_IR(arm11, ARM11_ITRSEL, -1);
arm11_add_debug_INST(arm11, opcode, NULL, TAP_RTI);
arm11_add_debug_INST(arm11, opcode, NULL, TAP_IDLE);
arm11_add_IR(arm11, ARM11_INTEST, -1);
@ -604,7 +604,7 @@ void arm11_run_instr_data_from_core(arm11_common_t * arm11, u32 opcode, u32 * da
{
do
{
arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, count ? TAP_RTI : TAP_PD);
arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, count ? TAP_IDLE : TAP_DRPAUSE);
jtag_execute_queue();
JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data, Ready, nRetry);
@ -699,11 +699,11 @@ void arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t
AddressOut = 0;
}
do
do
{
JTAG_DEBUG("SC7 <= Address %02x Data %08x nRW %d", AddressOut, DataOut, nRW);
arm11_add_dr_scan_vc(asizeof(chain7_fields), chain7_fields, TAP_PD);
arm11_add_dr_scan_vc(asizeof(chain7_fields), chain7_fields, TAP_DRPAUSE);
jtag_execute_queue();
JTAG_DEBUG("SC7 => Address %02x Data %08x Ready %d", AddressIn, DataIn, Ready);

2
src/target/arm720t.c
View File

@ -99,7 +99,7 @@ int arm720t_scan_cp15(target_t *target, u32 out, u32 *in, int instruction, int c
buf_set_u32(out_buf, 0, 32, flip_u32(out, 32));
jtag_add_end_state(TAP_PD);
jtag_add_end_state(TAP_DRPAUSE);
if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
{
return retval;

8
src/target/arm7_9_common.c
View File

@ -584,7 +584,7 @@ int arm7_9_execute_sys_speed(struct target_s *target)
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
/* set RESTART instruction */
jtag_add_end_state(TAP_RTI);
jtag_add_end_state(TAP_IDLE);
if (arm7_9->need_bypass_before_restart) {
arm7_9->need_bypass_before_restart = 0;
arm_jtag_set_instr(jtag_info, 0xf, NULL);
@ -630,7 +630,7 @@ int arm7_9_execute_fast_sys_speed(struct target_s *target)
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
/* set RESTART instruction */
jtag_add_end_state(TAP_RTI);
jtag_add_end_state(TAP_IDLE);
if (arm7_9->need_bypass_before_restart) {
arm7_9->need_bypass_before_restart = 0;
arm_jtag_set_instr(jtag_info, 0xf, NULL);
@ -1492,14 +1492,14 @@ int arm7_9_restart_core(struct target_s *target)
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* set RESTART instruction */
jtag_add_end_state(TAP_RTI);
jtag_add_end_state(TAP_IDLE);
if (arm7_9->need_bypass_before_restart) {
arm7_9->need_bypass_before_restart = 0;
arm_jtag_set_instr(jtag_info, 0xf, NULL);
}
arm_jtag_set_instr(jtag_info, 0x4, NULL);
jtag_add_runtest(1, TAP_RTI);
jtag_add_runtest(1, TAP_IDLE);
return jtag_execute_queue();
}

12
src/target/arm7tdmi.c
View File

@ -110,7 +110,7 @@ int arm7tdmi_examine_debug_reason(target_t *target)
u8 databus[4];
u8 breakpoint;
jtag_add_end_state(TAP_PD);
jtag_add_end_state(TAP_DRPAUSE);
fields[0].tap = arm7_9->jtag_info.tap;
fields[0].num_bits = 1;
@ -138,7 +138,7 @@ int arm7tdmi_examine_debug_reason(target_t *target)
}
arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL);
jtag_add_dr_scan(2, fields, TAP_PD);
jtag_add_dr_scan(2, fields, TAP_DRPAUSE);
if((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;
@ -149,7 +149,7 @@ int arm7tdmi_examine_debug_reason(target_t *target)
fields[1].in_value = NULL;
fields[1].out_value = databus;
jtag_add_dr_scan(2, fields, TAP_PD);
jtag_add_dr_scan(2, fields, TAP_DRPAUSE);
if (breakpoint & 1)
target->debug_reason = DBG_REASON_WATCHPOINT;
@ -179,7 +179,7 @@ static __inline int arm7tdmi_clock_out_inner(arm_jtag_t *jtag_info, u32 out, int
/* put an instruction in the ARM7TDMI pipeline or write the data bus, and optionally read data */
static __inline int arm7tdmi_clock_out(arm_jtag_t *jtag_info, u32 out, u32 *deprecated, int breakpoint)
{
jtag_add_end_state(TAP_PD);
jtag_add_end_state(TAP_DRPAUSE);
arm_jtag_scann(jtag_info, 0x1);
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
@ -192,7 +192,7 @@ int arm7tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
int retval = ERROR_OK;
scan_field_t fields[2];
jtag_add_end_state(TAP_PD);
jtag_add_end_state(TAP_DRPAUSE);
if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
{
return retval;
@ -253,7 +253,7 @@ int arm7tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size,
int retval = ERROR_OK;
scan_field_t fields[2];
jtag_add_end_state(TAP_PD);
jtag_add_end_state(TAP_DRPAUSE);
if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
{
return retval;

6
src/target/arm920t.c
View File

@ -106,7 +106,7 @@ int arm920t_read_cp15_physical(target_t *target, int reg_addr, u32 *value)
u8 reg_addr_buf = reg_addr & 0x3f;
u8 nr_w_buf = 0;
jtag_add_end_state(TAP_RTI);
jtag_add_end_state(TAP_IDLE);
arm_jtag_scann(jtag_info, 0xf);
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
@ -178,7 +178,7 @@ int arm920t_write_cp15_physical(target_t *target, int reg_addr, u32 value)
buf_set_u32(value_buf, 0, 32, value);
jtag_add_end_state(TAP_RTI);
jtag_add_end_state(TAP_IDLE);
arm_jtag_scann(jtag_info, 0xf);
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
@ -243,7 +243,7 @@ int arm920t_execute_cp15(target_t *target, u32 cp15_opcode, u32 arm_opcode)
u8 nr_w_buf = 0;
u8 cp15_opcode_buf[4];
jtag_add_end_state(TAP_RTI);
jtag_add_end_state(TAP_IDLE);
arm_jtag_scann(jtag_info, 0xf);
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);

4
src/target/arm926ejs.c
View File

@ -132,7 +132,7 @@ int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u3
buf_set_u32(address_buf, 0, 14, address);
jtag_add_end_state(TAP_RTI);
jtag_add_end_state(TAP_IDLE);
if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
{
return retval;
@ -222,7 +222,7 @@ int arm926ejs_cp15_write(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u
buf_set_u32(address_buf, 0, 14, address);
buf_set_u32(value_buf, 0, 32, value);
jtag_add_end_state(TAP_RTI);
jtag_add_end_state(TAP_IDLE);
if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
{
return retval;

4
src/target/arm966e.c
View File

@ -178,7 +178,7 @@ int arm966e_read_cp15(target_t *target, int reg_addr, u32 *value)
u8 reg_addr_buf = reg_addr & 0x3f;
u8 nr_w_buf = 0;
jtag_add_end_state(TAP_RTI);
jtag_add_end_state(TAP_IDLE);
if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
{
return retval;
@ -246,7 +246,7 @@ int arm966e_write_cp15(target_t *target, int reg_addr, u32 value)
buf_set_u32(value_buf, 0, 32, value);
jtag_add_end_state(TAP_RTI);
jtag_add_end_state(TAP_IDLE);
if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
{
return retval;

12
src/target/arm9tdmi.c
View File

@ -125,7 +125,7 @@ int arm9tdmi_examine_debug_reason(target_t *target)
u8 instructionbus[4];
u8 debug_reason;
jtag_add_end_state(TAP_PD);
jtag_add_end_state(TAP_DRPAUSE);
fields[0].tap = arm7_9->jtag_info.tap;
fields[0].num_bits = 32;
@ -163,7 +163,7 @@ int arm9tdmi_examine_debug_reason(target_t *target)
}
arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL);
jtag_add_dr_scan(3, fields, TAP_PD);
jtag_add_dr_scan(3, fields, TAP_DRPAUSE);
if((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;
@ -176,7 +176,7 @@ int arm9tdmi_examine_debug_reason(target_t *target)
fields[2].in_value = NULL;
fields[2].out_value = instructionbus;
jtag_add_dr_scan(3, fields, TAP_PD);
jtag_add_dr_scan(3, fields, TAP_DRPAUSE);
if (debug_reason & 0x4)
if (debug_reason & 0x2)
@ -207,7 +207,7 @@ int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int s
if (sysspeed)
buf_set_u32(&sysspeed_buf, 2, 1, 1);
jtag_add_end_state(TAP_PD);
jtag_add_end_state(TAP_DRPAUSE);
if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
{
return retval;
@ -282,7 +282,7 @@ int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
int retval = ERROR_OK;;
scan_field_t fields[3];
jtag_add_end_state(TAP_PD);
jtag_add_end_state(TAP_DRPAUSE);
if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
{
return retval;
@ -354,7 +354,7 @@ int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size,
int retval = ERROR_OK;
scan_field_t fields[3];
jtag_add_end_state(TAP_PD);
jtag_add_end_state(TAP_DRPAUSE);
if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
{
return retval;

4
src/target/cortex_swjdp.c
View File

@ -64,7 +64,7 @@ int swjdp_scan(arm_jtag_t *jtag_info, u8 instr, u8 reg_addr, u8 RnW, u8 *outvalu
scan_field_t fields[2];
u8 out_addr_buf;
jtag_add_end_state(TAP_RTI);
jtag_add_end_state(TAP_IDLE);
arm_jtag_set_instr(jtag_info, instr, NULL);
fields[0].tap = jtag_info->tap;
@ -100,7 +100,7 @@ int swjdp_scan_u32(arm_jtag_t *jtag_info, u8 instr, u8 reg_addr, u8 RnW, u32 out
u8 out_value_buf[4];
u8 out_addr_buf;
jtag_add_end_state(TAP_RTI);
jtag_add_end_state(TAP_IDLE);
arm_jtag_set_instr(jtag_info, instr, NULL);
fields[0].tap = jtag_info->tap;

10
src/target/embeddedice.c
View File

@ -246,7 +246,7 @@ int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
u8 field1_out[1];
u8 field2_out[1];
jtag_add_end_state(TAP_RTI);
jtag_add_end_state(TAP_IDLE);
arm_jtag_scann(ice_reg->jtag_info, 0x2);
arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);
@ -309,7 +309,7 @@ int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size)
u8 field1_out[1];
u8 field2_out[1];
jtag_add_end_state(TAP_RTI);
jtag_add_end_state(TAP_IDLE);
arm_jtag_scann(jtag_info, 0x2);
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
@ -400,7 +400,7 @@ void embeddedice_write_reg(reg_t *reg, u32 value)
LOG_DEBUG("%i: 0x%8.8x", ice_reg->addr, value);
jtag_add_end_state(TAP_RTI);
jtag_add_end_state(TAP_IDLE);
arm_jtag_scann(ice_reg->jtag_info, 0x2);
arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);
@ -426,7 +426,7 @@ int embeddedice_send(arm_jtag_t *jtag_info, u32 *data, u32 size)
u8 field1_out[1];
u8 field2_out[1];
jtag_add_end_state(TAP_RTI);
jtag_add_end_state(TAP_IDLE);
arm_jtag_scann(jtag_info, 0x2);
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
@ -495,7 +495,7 @@ int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, u32 timeout)
else
return ERROR_INVALID_ARGUMENTS;
jtag_add_end_state(TAP_RTI);
jtag_add_end_state(TAP_IDLE);
arm_jtag_scann(jtag_info, 0x2);
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);

6
src/target/etb.c
View File

@ -184,7 +184,7 @@ int etb_read_ram(etb_t *etb, u32 *data, int num_frames)
scan_field_t fields[3];
int i;
jtag_add_end_state(TAP_RTI);
jtag_add_end_state(TAP_IDLE);
etb_scann(etb, 0x0);
etb_set_instr(etb, 0xc);
@ -255,7 +255,7 @@ int etb_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
LOG_DEBUG("%i", etb_reg->addr);
jtag_add_end_state(TAP_RTI);
jtag_add_end_state(TAP_IDLE);
etb_scann(etb_reg->etb, 0x0);
etb_set_instr(etb_reg->etb, 0xc);
@ -351,7 +351,7 @@ int etb_write_reg(reg_t *reg, u32 value)
LOG_DEBUG("%i: 0x%8.8x", etb_reg->addr, value);
jtag_add_end_state(TAP_RTI);
jtag_add_end_state(TAP_IDLE);
etb_scann(etb_reg->etb, 0x0);
etb_set_instr(etb_reg->etb, 0xc);

4
src/target/etm.c
View File

@ -335,7 +335,7 @@ int etm_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
LOG_DEBUG("%i", etm_reg->addr);
jtag_add_end_state(TAP_RTI);
jtag_add_end_state(TAP_IDLE);
arm_jtag_scann(etm_reg->jtag_info, 0x6);
arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
@ -426,7 +426,7 @@ int etm_write_reg(reg_t *reg, u32 value)
LOG_DEBUG("%i: 0x%8.8x", etm_reg->addr, value);
jtag_add_end_state(TAP_RTI);
jtag_add_end_state(TAP_IDLE);
arm_jtag_scann(etm_reg->jtag_info, 0x6);
arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);

2
src/target/feroceon.c
View File

@ -127,7 +127,7 @@ int feroceon_dummy_clock_out(arm_jtag_t *jtag_info, u32 instr)
buf_set_u32(instr_buf, 0, 32, flip_u32(instr, 32));
jtag_add_end_state(TAP_PD);
jtag_add_end_state(TAP_DRPAUSE);
arm_jtag_scann(jtag_info, 0x1);
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);

6
src/target/mips_ejtag.c
View File

@ -65,7 +65,7 @@ int mips_ejtag_get_idcode(mips_ejtag_t *ejtag_info, u32 *idcode, in_handler_t ha
{
scan_field_t field;
jtag_add_end_state(TAP_RTI);
jtag_add_end_state(TAP_IDLE);
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IDCODE, NULL);
@ -92,7 +92,7 @@ int mips_ejtag_get_impcode(mips_ejtag_t *ejtag_info, u32 *impcode, in_handler_t
{
scan_field_t field;
jtag_add_end_state(TAP_RTI);
jtag_add_end_state(TAP_IDLE);
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IMPCODE, NULL);
@ -202,7 +202,7 @@ int mips_ejtag_config_step(mips_ejtag_t *ejtag_info, int enable_step)
int mips_ejtag_enter_debug(mips_ejtag_t *ejtag_info)
{
u32 ejtag_ctrl;
jtag_add_end_state(TAP_RTI);
jtag_add_end_state(TAP_IDLE);
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
/* set debug break bit */

10
src/target/mips_m4k.c
View File

@ -163,7 +163,7 @@ int mips_m4k_poll(target_t *target)
u32 ejtag_ctrl = ejtag_info->ejtag_ctrl;
/* read ejtag control reg */
jtag_add_end_state(TAP_RTI);
jtag_add_end_state(TAP_IDLE);
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
@ -173,7 +173,7 @@ int mips_m4k_poll(target_t *target)
{
/* we have detected a reset, clear flag
* otherwise ejtag will not work */
jtag_add_end_state(TAP_RTI);
jtag_add_end_state(TAP_IDLE);
ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_ROCC;
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
@ -186,7 +186,7 @@ int mips_m4k_poll(target_t *target)
{
if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
{
jtag_add_end_state(TAP_RTI);
jtag_add_end_state(TAP_IDLE);
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL);
target->state = TARGET_HALTED;
@ -279,12 +279,12 @@ int mips_m4k_assert_reset(target_t *target)
if (target->reset_halt)
{
/* use hardware to catch reset */
jtag_add_end_state(TAP_RTI);
jtag_add_end_state(TAP_IDLE);
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_EJTAGBOOT, NULL);
}
else
{
jtag_add_end_state(TAP_RTI);
jtag_add_end_state(TAP_IDLE);
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL);
}

64
src/target/xscale.c
View File

@ -252,7 +252,7 @@ int xscale_read_dcsr(target_t *target)
u8 field2_check_value = 0x0;
u8 field2_check_mask = 0x1;
jtag_add_end_state(TAP_PD);
jtag_add_end_state(TAP_DRPAUSE);
xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dcsr);
buf_set_u32(&field0, 1, 1, xscale->hold_rst);
@ -300,7 +300,7 @@ int xscale_read_dcsr(target_t *target)
fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
fields[1].in_value = NULL;
jtag_add_end_state(TAP_RTI);
jtag_add_end_state(TAP_IDLE);
jtag_add_dr_scan(3, fields, -1);
@ -332,9 +332,9 @@ int xscale_receive(target_t *target, u32 *buffer, int num_words)
int i;
path[0] = TAP_SDS;
path[1] = TAP_CD;
path[2] = TAP_SD;
path[0] = TAP_DRSELECT;
path[1] = TAP_DRCAPTURE;
path[2] = TAP_DRSHIFT;
fields[0].tap = xscale->jtag_info.tap;
fields[0].num_bits = 3;
@ -362,9 +362,9 @@ int xscale_receive(target_t *target, u32 *buffer, int num_words)
fields[2].in_value = NULL;
jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL);
jtag_add_end_state(TAP_RTI);
jtag_add_end_state(TAP_IDLE);
xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgtx);
jtag_add_runtest(1, -1); /* ensures that we're in the TAP_RTI state as the above could be a no-op */
jtag_add_runtest(1, -1); /* ensures that we're in the TAP_IDLE state as the above could be a no-op */
/* repeat until all words have been collected */
int attempts=0;
@ -379,7 +379,7 @@ int xscale_receive(target_t *target, u32 *buffer, int num_words)
fields[1].in_handler_priv = (u8*)&field1[i];
jtag_add_pathmove(3, path);
jtag_add_dr_scan(3, fields, TAP_RTI);
jtag_add_dr_scan(3, fields, TAP_IDLE);
words_scheduled++;
}
@ -442,20 +442,20 @@ int xscale_read_tx(target_t *target, int consume)
u8 field2_check_value = 0x0;
u8 field2_check_mask = 0x1;
jtag_add_end_state(TAP_RTI);
jtag_add_end_state(TAP_IDLE);
xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgtx);
path[0] = TAP_SDS;
path[1] = TAP_CD;
path[2] = TAP_SD;
path[0] = TAP_DRSELECT;
path[1] = TAP_DRCAPTURE;
path[2] = TAP_DRSHIFT;
noconsume_path[0] = TAP_SDS;
noconsume_path[1] = TAP_CD;
noconsume_path[2] = TAP_E1D;
noconsume_path[3] = TAP_PD;
noconsume_path[4] = TAP_E2D;
noconsume_path[5] = TAP_SD;
noconsume_path[0] = TAP_DRSELECT;
noconsume_path[1] = TAP_DRCAPTURE;
noconsume_path[2] = TAP_DREXIT1;
noconsume_path[3] = TAP_DRPAUSE;
noconsume_path[4] = TAP_DREXIT2;
noconsume_path[5] = TAP_DRSHIFT;
fields[0].tap = xscale->jtag_info.tap;
fields[0].num_bits = 3;
@ -499,7 +499,7 @@ int xscale_read_tx(target_t *target, int consume)
jtag_add_pathmove(sizeof(noconsume_path)/sizeof(*noconsume_path), noconsume_path);
}
jtag_add_dr_scan(3, fields, TAP_RTI);
jtag_add_dr_scan(3, fields, TAP_IDLE);
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
@ -551,7 +551,7 @@ int xscale_write_rx(target_t *target)
u8 field2_check_value = 0x0;
u8 field2_check_mask = 0x1;
jtag_add_end_state(TAP_RTI);
jtag_add_end_state(TAP_IDLE);
xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgrx);
@ -588,7 +588,7 @@ int xscale_write_rx(target_t *target)
LOG_DEBUG("polling RX");
for (;;)
{
jtag_add_dr_scan(3, fields, TAP_RTI);
jtag_add_dr_scan(3, fields, TAP_IDLE);
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
@ -617,7 +617,7 @@ int xscale_write_rx(target_t *target)
/* set rx_valid */
field2 = 0x1;
jtag_add_dr_scan(3, fields, TAP_RTI);
jtag_add_dr_scan(3, fields, TAP_IDLE);
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
@ -640,7 +640,7 @@ int xscale_send(target_t *target, u8 *buffer, int count, int size)
int done_count = 0;
jtag_add_end_state(TAP_RTI);
jtag_add_end_state(TAP_IDLE);
xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgrx);
@ -683,7 +683,7 @@ int xscale_send(target_t *target, u8 *buffer, int count, int size)
3,
bits,
t,
TAP_RTI);
TAP_IDLE);
buffer += size;
}
@ -726,7 +726,7 @@ int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk)
if (ext_dbg_brk != -1)
xscale->external_debug_break = ext_dbg_brk;
jtag_add_end_state(TAP_RTI);
jtag_add_end_state(TAP_IDLE);
xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dcsr);
buf_set_u32(&field0, 1, 1, xscale->hold_rst);
@ -796,7 +796,7 @@ int xscale_load_ic(target_t *target, int mini, u32 va, u32 buffer[8])
LOG_DEBUG("loading miniIC at 0x%8.8x", va);
jtag_add_end_state(TAP_RTI);
jtag_add_end_state(TAP_IDLE);
xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.ldic); /* LDIC */
/* CMD is b010 for Main IC and b011 for Mini IC */
@ -859,7 +859,7 @@ int xscale_invalidate_ic_line(target_t *target, u32 va)
scan_field_t fields[2];
jtag_add_end_state(TAP_RTI);
jtag_add_end_state(TAP_IDLE);
xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.ldic); /* LDIC */
/* CMD for invalidate IC line b000, bits [6:4] b000 */
@ -1597,7 +1597,7 @@ int xscale_assert_reset(target_t *target)
/* select DCSR instruction (set endstate to R-T-I to ensure we don't
* end up in T-L-R, which would reset JTAG
*/
jtag_add_end_state(TAP_RTI);
jtag_add_end_state(TAP_IDLE);
xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dcsr);
/* set Hold reset, Halt mode and Trap Reset */
@ -1620,7 +1620,7 @@ int xscale_assert_reset(target_t *target)
if (target->reset_halt)
{
int retval;
int retval;
if ((retval = target_halt(target))!=ERROR_OK)
return retval;
}
@ -1671,7 +1671,7 @@ int xscale_deassert_reset(target_t *target)
/* wait 300ms; 150 and 100ms were not enough */
jtag_add_sleep(300*1000);
jtag_add_runtest(2030, TAP_RTI);
jtag_add_runtest(2030, TAP_IDLE);
jtag_execute_queue();
/* set Hold reset, Halt mode and Trap Reset */
@ -1734,7 +1734,7 @@ int xscale_deassert_reset(target_t *target)
xscale_load_ic(target, 1, 0x0, xscale->low_vectors);
xscale_load_ic(target, 1, 0xffff0000, xscale->high_vectors);
jtag_add_runtest(30, TAP_RTI);
jtag_add_runtest(30, TAP_IDLE);
jtag_add_sleep(100000);
@ -3381,7 +3381,7 @@ int xscale_handle_idcache_command(command_context_t *cmd_ctx, char *cmd, char **
command_print(cmd_ctx, "icache %s", (xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled) ? "enabled" : "disabled");
if (dcache)
command_print(cmd_ctx, "dcache %s", (xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) ? "enabled" : "disabled");
command_print(cmd_ctx, "dcache %s", (xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) ? "enabled" : "disabled");
return ERROR_OK;
}

30
src/xsvf/xsvf.c
View File

@ -62,9 +62,9 @@ int xenddr = 0;
enum tap_state xsvf_to_tap[] =
{
TAP_TLR, TAP_RTI,
TAP_SDS, TAP_CD, TAP_SD, TAP_E1D, TAP_PD, TAP_E2D, TAP_UD,
TAP_SIS, TAP_CI, TAP_SI, TAP_E1I, TAP_PI, TAP_E2I, TAP_UI,
TAP_RESET, TAP_IDLE,
TAP_DRSELECT, TAP_DRCAPTURE, TAP_DRSHIFT, TAP_DREXIT1, TAP_DRPAUSE, TAP_DREXIT2, TAP_DRUPDATE,
TAP_IRSELECT, TAP_IRCAPTURE, TAP_IRSHIFT, TAP_IREXIT1, TAP_IRPAUSE, TAP_IREXIT2, TAP_IRUPDATE,
};
int tap_to_xsvf[] =
@ -86,10 +86,10 @@ void xsvf_add_statemove(enum tap_state state)
enum tap_state curstate = cmd_queue_cur_state;
u8 move = TAP_MOVE(cmd_queue_cur_state, state);
if ((state != TAP_TLR) && (state == cmd_queue_cur_state))
if ((state != TAP_RESET) && (state == cmd_queue_cur_state))
return;
if(state==TAP_TLR)
if(state==TAP_RESET)
{
jtag_add_tlr();
return;
@ -239,9 +239,9 @@ int handle_xsvf_command(struct command_context_s *cmd_ctx, char *cmd, char **arg
field.in_handler = NULL;
field.in_handler_priv = NULL;
if (tap == NULL)
jtag_add_plain_ir_scan(1, &field, TAP_PI);
jtag_add_plain_ir_scan(1, &field, TAP_IRPAUSE);
else
jtag_add_ir_scan(1, &field, TAP_PI);
jtag_add_ir_scan(1, &field, TAP_IRPAUSE);
if (jtag_execute_queue() != ERROR_OK)
{
tdo_mismatch = 1;
@ -254,7 +254,7 @@ int handle_xsvf_command(struct command_context_s *cmd_ctx, char *cmd, char **arg
jtag_add_runtest(xruntest, xsvf_to_tap[xendir]);
else
{
xsvf_add_statemove(TAP_RTI);
xsvf_add_statemove(TAP_IDLE);
jtag_add_sleep(xruntest);
xsvf_add_statemove(xsvf_to_tap[xendir]);
}
@ -279,9 +279,9 @@ int handle_xsvf_command(struct command_context_s *cmd_ctx, char *cmd, char **arg
field.in_value = NULL;
jtag_set_check_value(&field, dr_in_buf, dr_in_mask, NULL);
if (tap == NULL)
jtag_add_plain_dr_scan(1, &field, TAP_PD);
jtag_add_plain_dr_scan(1, &field, TAP_DRPAUSE);
else
jtag_add_dr_scan(1, &field, TAP_PD);
jtag_add_dr_scan(1, &field, TAP_DRPAUSE);
if (jtag_execute_queue() != ERROR_OK)
{
tdo_mismatch = 1;
@ -293,7 +293,7 @@ int handle_xsvf_command(struct command_context_s *cmd_ctx, char *cmd, char **arg
jtag_add_runtest(xruntest, xsvf_to_tap[xenddr]);
else
{
xsvf_add_statemove(TAP_RTI);
xsvf_add_statemove(TAP_IDLE);
jtag_add_sleep(xruntest);
xsvf_add_statemove(xsvf_to_tap[xenddr]);
}
@ -353,9 +353,9 @@ int handle_xsvf_command(struct command_context_s *cmd_ctx, char *cmd, char **arg
field.in_value = NULL;
jtag_set_check_value(&field, dr_in_buf, dr_in_mask, NULL);
if (tap == NULL)
jtag_add_plain_dr_scan(1, &field, TAP_PD);
jtag_add_plain_dr_scan(1, &field, TAP_DRPAUSE);
else
jtag_add_dr_scan(1, &field, TAP_PD);
jtag_add_dr_scan(1, &field, TAP_DRPAUSE);
if (jtag_execute_queue() != ERROR_OK)
{
tdo_mismatch = 1;
@ -367,7 +367,7 @@ int handle_xsvf_command(struct command_context_s *cmd_ctx, char *cmd, char **arg
jtag_add_runtest(xruntest, xsvf_to_tap[xenddr]);
else
{
xsvf_add_statemove(TAP_RTI);
xsvf_add_statemove(TAP_IDLE);
jtag_add_sleep(xruntest);
xsvf_add_statemove(xsvf_to_tap[xenddr]);
}
@ -423,7 +423,7 @@ int handle_xsvf_command(struct command_context_s *cmd_ctx, char *cmd, char **arg
*/
for(i=0,lasti=0;i<path_len;i++)
{
if(path[i]==TAP_TLR)
if(path[i]==TAP_RESET)
{
if(i>lasti)
{